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data acquisition system basis chip zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 1 april 20, 2016 brief description the zssc1750 and zssc1751 are system basis chip s (sbc s ) with a dual - channel adc for battery sens ing/manage ment in automotive, industrial, and medical systems . the zssc1750 and zssc1751 feature an spi interface ; in addition , the zssc1750 has a n integrated lin 2.1 transceiver. one of the two input channels measures the battery curren t i bat via the voltage drop at the external shunt resistor. the second channel measure s the battery voltage v bat and th e temperature. by simultaneous ly measur ing v bat and i bat , it is possible to determine dynamically the internal resistance of the battery, rdi, whi ch is correlated with the state - of - health (soh) of the battery. by integrating i bat , it is possible to determine the state - of - charge (soc) and the state - of - function (sof) of the battery. during sleep mode, the system makes periodic measurements to monitor the dis charge of the battery. meas urement cycles are controlled by user software and include various wake - up conditions. the zssc1750 /51 is optimized for ultra - low power consumption drawing only 60a or less in this mode. features ? two h igh - precision 24- bit sigma - delta adc s (18 - bit with no missing codes) ; sample rate: 1hz to 16khz ? o n - chip voltage reference (5ppm/k typical ) ? current channel ? i bat offset error: 10ma ? i bat resolution: 1ma ? programmable gain: 4 to 512 ? max . differential input stage input range: 300mv ? voltage channel ? input range: 4 to 28.8v ? voltage accuracy: 60ppm fsr * = 1.73 mv ? temperature channel ? external temperature sensor (ntc) ? factory - calibrated internal temp . sensor : 2c ? lin 2.1/sae j2602 - 1 t ransceiver (zssc1750 only) ? typical c urrent consumption ? normal mode: 1 2 ma ? sleep mode: 60 a benefits ? integrated, precision measurement solution for accurate prediction of battery state of health (soh), state of charge (soc), or state of function (sof) ? robust power - on - reset (por) concept for harsh automotive environment s ? on - ch ip precision oscillator accuracy: 1% ? on - chip low - power oscillator ? only a few external components needed ? easy communication via spi i nterface ? p ower supply , interrupt , and reset signals for external microcontroller ? w atchdog timer with dedicated oscillator ? industry?s smallest footprint allows minimal module size and cost ? aec - q100 qualified solution available support ? evaluation kit ? application notes physical characteristics ? o pe ration temperature up to - 40c to +125 c ? supply voltage: 4.2 to 18v ? small footprint package: pqfn 36 6x6 mm * fsr = full - scale range. basic zssc1750 /51 application circuit vbat inn inp - car c hassis g round lin r shunt vdde + - vssa vsse + battery spi t o h arness vdd a nth spi vss vdd vddp rx tx zssc 1750 / 51 c lin - i / f ( zssc 1750 ) irq n irq 3 . 3 v , < 30 ma mcu _ rstn rst i / f interface t o h ost ( e . g . can ) mcu _ clk clk ( opt .) ntl ntc
data acquisition system basis chip zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 2 april 20, 2016 mcu _ clk irq n vddp vddc zssc 1 750 / 51 analog front end sbc common ground pga mux v bat lin vddp _ reg bg _ ref wd _ timer vddc _ reg osc gp _ timer lp _ reg vdda _ reg digital filter config register result register digital filter calibration data path shunt + ? battery sd _ adc sd _ adc r ref ntc lin _ phys ( 1 ) r x d t x d csn sclk miso mosi vdde vdda inp inn vbat nth lin analog block digital block sbc _ pmu mcu _ rstn sleepn irq _ ctrl spi wdt _ dis 1 ) available in zssc 1750 only nt l applications ? intelligent battery monitoring in automotive applications; start/stop systems, e - bikes, scooters, and e - carts ? battery monitoring in industrial, medical and photovoltaic applications; ? high precision data acquisition z ssc 175 0 /51 block diagram rbat 100 rinn 22 0 rinp 22 0 rdde 2 . 2 vdde inn vsse vssa inp vpp trstn vdda nth vbat vddp vddc test sleepn vddl lin vssa tms tck sto testl testh vsslin vssn rxd txd mcu _ rstn irqn csn sclk mosi cin 10 0 nf cddl 10 nf rshunt 100 cntc 470 pf ddde bas 2 1 rref 75 k rntc 10 k cdda 470 nf cinn 1 0 nf cinp 1 0 nf cdde 1 10 f cbat 100 nf n . c . rxd chassis gnd bat + bat - tck tms trstn n . c . sto zssc 1750 cdde 2 10 0 nf ntl vss r cddp 2 . 2 f cdd c 2 . 2 f sleepn mcu _ clk wdt _ dis wdt _ dis mcu _ clk miso txd mcu _ rstn irqn csn sclk mosi miso clin 220 pf lin zssc 1750 typical application circuit 1 rbat 100 rinn 220 rinp 220 rdde 2.2 vdde inn vsse vssa inp vpp trstn vdda nth vbat vddp vddc test sleepn vddl nc vssa tms tck sto testl testh vss vssn open mcu_rstn irqn csn sclk mosi cin 100nf cddl 10nf rshunt 100? cntc 470pf ddde bas21 rref 75k rntc 10k cdda 470nf cinn 10nf cinp 10nf cdde1 10f cbat 100nf n.c . nc chassis gnd bat+ bat - tck tms trstn n.c . sto zssc1751 cdde2 100nf ntl vssr cddp 2.2f cddc 2. 2f sleepn mcu_clk wdt_dis wdt_dis mcu_clk miso mcu_rstn irqn csn sclk mosi miso zssc1751 typical application circuit nc open vddp 1 ordering information product sales code description package zssc1750 ea3 r zssc1750 battery sensing sbc ? temperature range: - 40c to 125c pqfn36 6x6 mm, reel ZSSC1751EA3R zssc1751 battery sensing sbc ? temperature range: - 40c to 125c pqfn36 6x6 mm, reel zssc1750kit v1.1 zssc1750/51 evaluation kit: modular evaluation and development board for zssc1750/51, 3 ic samples, and usb cable (software and documentation can be downloaded from www.idt.com ) corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800- 345- 7015 or 408 - 284- 8200 fax: 408 - 284- 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. performance specifications and operating p arameters of the described products are determined in an independent state and are not guaranteed to perform the same way whe n installed in customer products. the information contained herein is provided without representation or warranty of any kind, whet her express or implied, including, but not limited to, the suitability of idt's products for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integ rated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the unit ed states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for dat asheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 3 april 20, 2016 contents 1 ic characteristics ............................................................................................................................................. 8 1.1 absolute maximum ratings ....................................................................................................................... 8 1.2 recommended operating conditions ....................................................................................................... 9 1.3 electrical parameters .............................................................................................................................. 10 1.4 timing parameters .................................................................................................................................. 18 2 circuit description .......................................................................................................................................... 21 2.1 ov erview .................................................................................................................................................. 21 2.2 sbc - to - mcu interface pins ..................................................................................................................... 22 2.2.1 digital i/os ........................................................................................................................................ 23 2.2.2 exte rnal microcontroller (mcu) supply pins .................................................................................... 23 2.2.3 sleepn power state indicator pin .................................................................................................. 23 2.3 system power states .............................................................................................................................. 24 2.3.1 full power state (fp) ....................................................................................................................... 24 2.3.2 low power state (lp) ...................................................................................................................... 24 2.3.3 ultra low power state (ulp) ........................................................................................................... 25 2.3.4 off power state .............................................................................................................................. 25 3 zssc1750/51 functional block descriptions ................................................................................................ 26 3.1 serial peripheral interface (spi slave) .................................................................................................... 26 3.1.1 spi protocol ...................................................................................................................................... 26 3.2 sbc register map (result register block and config register block) ................................ 28 3.3 zssc1750/51 clock and reset logic ..................................................................................................... 33 3.3.1 clock sources .................................................................................................................................. 33 3.3.2 trimming the low - power oscillator ................................................................................................. 34 3.3.3 clock trimming and configuration registers ................................................................................... 35 3.3.4 resets .............................................................................................................................................. 37 3.4 sbc watchdog timer (wd_timer block) ............................................................................................. 39 3.4.1 watchdog registers ......................................................................................................................... 41 3.5 sbc sleep timer (gp_timer block) ..................................................................................................... 43 3.5.1 sleep timer registers ...................................................................................................................... 44 3.6 sbc interrupt controller (irq_ctrl block) ........................................................................................... 45 3.7 sbc power management unit (sbc_pmu block) .................................................................................. 49 3.7.1 fp state ............................................................................................................................................ 50 3.7.2 lp and ulp states ........................................................................................................................... 51 3.7. 3 off state ......................................................................................................................................... 60 3.7.4 registers for power configuration and the discreet current measurement count ......................... 61 3.8 zssc1750/51 adc unit .......................................................................................................................... 63 3.8. 1 adc clocks ...................................................................................................................................... 64 3.8.2 adc data path ................................................................................................................................. 69 3.8.3 adc operating modes and result registers ................................................................................... 74 3.8.4 adc control and conversion timing ............................................................................................... 86
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 4 april 20, 2016 3.8.5 diagnostic features .......................................................................................................................... 96 3.8.6 digital features ................................................................................................................................ 97 3.9 sbc lin support logic (for zssc1750 only) ....................................................................................... 100 3.9.1 lin wakeup detection ................................................................................................................... 100 3.9.2 txd timeout detection .................................................................................................................. 100 3.9.3 lin short detection ........................................................................................................................ 101 3.9.4 lin testing ..................................................................................................................................... 102 3.10 zssc1750/51 otp (config register) ........................................................................................... 104 3.11 miscellaneous registers ........................................................................................................................ 105 3.12 voltage regulators ................................................................................................................................ 108 3.12.1 vdde .............................................................................................................................................. 108 3.12.2 vbat .............................................................................................................................................. 108 3.12.3 vdda .............................................................................................................................................. 108 3.12.4 vddl .............................................................................................................................................. 109 3.12.5 vddp .............................................................................................................................................. 109 3.12.6 vddc ............................................................................................................................................. 109 4 esd / emc ................................................................................................................................................... 110 4.1 electrostatic discharge .......................................................................................................................... 110 4.2 power system ripple factor ................................................................................................................. 110 4.3 application circuit examples for emc conformance ............................................................................ 111 5 pin configuration and package .................................................................................................................... 112 6 ordering information .................................................................................................................................... 115 7 related documents ...................................................................................................................................... 115 8 glossa ry ....................................................................................................................................................... 115 9 document revision history .......................................................................................................................... 116 list of figures figure 1.1 measurement method for determining vddp pin current capability .............................................. 17 figure 1.2 spi protocol timing .......................................................................................................................... 19 figure 1.3 zssc1750/51 power - up and power - down sequence .................................................................... 20 figure 2.1 functional block diagram ................................................................................................................. 21 figure 2.2 zssc1750/51 digital io interface .................................................................................................... 22 figure 2.3 zssc1750/51 power states ............................................................................................................. 24 figure 3.1 read and write burst access to the sbc ........................................................................................ 27 figure 3.2 structure of the watchdog timer ...................................................................................................... 39 figure 3.3 structure of the sleep timer ............................................................................................................. 43 figure 3.4 generation of interrupt and wake - up ............................................................................................... 46 figure 3.5 lp/ulp state without any measurements ........................................................................................ 52 figure 3.6 lp/ulp state performing only current measurements ................................................................... 54
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 5 april 20, 2016 figure 3.7 lp/ulp state performing current, voltage, and temperature measurements with disccvtcnt == 2 ..................................................................................................................... 56 figure 3.8 lp/ulp state performing current, voltage, and temperature measurements with disccvtcnt == 5 ..................................................................................................................... 56 figure 3.9 lp/ulp state performing current, voltage, and temperature measurements with disccvtcnt == 1 ..................................................................................................................... 57 figure 3.10 lp/ulp state performing continuous current - only measurements ............................................... 58 figure 3.11 performing continuous current and voltage measurements during lp/ulp state ......................... 60 figure 3.12 functional block diagram of the analog measurement subsystem ................................................ 64 figure 3.13 fp adc clocking scheme for sdmpos = sdmpos2 = 2; sdmclkdivfp = 1; sdmchopclkdiv = 0 ........................................................................................................................ 66 figure 3.14 fp adc clocking for sdmpos = 1 and sdmpos2 = 4; sdmclkdivfp = 1; sdmchopclkdiv = 0 ... 66 figure 3.15 fp adc clocking for sdmpos = 3 and sdmpos2 = 0; sdmclkdivfp = 1; sdmchopclkdiv = 0 ... 67 figure 3.16 fp adc clocking for sdmpos = 0 and sdmpos2 = 3; sdmclkdivfp = 1; sdmchopclkdiv = 0 ... 67 figure 3.17 lp/ulp adc clocking scheme; sdmclkdivlp = 5; sdmchopclkdiv = 0 ................................... 68 figure 3.18 functional block diagram of the digital adc data path .................................................................. 69 figure 3.19 da ta post correction ........................................................................................................................ 70 figure 3.20 data representation through data post correction including over - range and overflow levels ... 71 figure 3.21 common enable for the ?set overrange? and ?set overflow? interrupt strobes for current .............. 72 figure 3.22 individual srcs ................................................................................................................................ 87 figure 3.23 individual mrcs (example for result counter of 3) ........................................................................ 87 figure 3.24 continuous srcs ............................................................................................................................. 88 figure 3.25 continuous mrcs (example for result counter of 3) ..................................................................... 88 figure 3.26 stopping continuous srcs ............................................................................................................. 89 figure 3.27 stopping continuous mrcs (example for result counter of 3) ...................................................... 89 figure 3.28 interrupting a continuous srcs ...................................................................................................... 90 figure 3.29 interrupting a continuous mrcs (example for result counter of 3) ............................................... 90 figure 3.30 signal behavior of adcmode ............................................................................................................ 91 figure 3.31 timing for current, voltage, and internal temperature measurements without chopping for different configurations of the average filter .................................................................................. 93 figure 3.32 timing for external temperature measurements without chopping when no average filter is enabled ............................................................................................................ 94 figure 3.33 timing for current, voltage, and internal temperature measurements using chopping ................. 95 figure 3.34 timing for external temperature measurements using chopping ................................................... 96 figure 3.35 usage of register adccaccth for the digital adc bist ................................................................ 98 figure 3.36 bit stream of adc interface test at sto pad ................................................................................. 99 figure 3.37 protection logic of the lin txd line ............................................................................................. 100 figure 3.38 waveform showing the gating principle for non - zero values of linshortdelay...................... 101 figure 4.1 optional external components for zssc1750 ............................................................................... 111 figure 4.2 optional external components for zssc1751 ............................................................................... 111 figure 5.1 zssc1750/51 pqfn36 6x6mm package pin - out (top view) ....................................................... 112 figure 5.2 package drawing of the zs sc1750/51 .......................................................................................... 114
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 6 april 20, 2016 list of tables table 1.1 absolute maximum ratings (referenced to vsse) ............................................................................. 8 table 1.2 operating conditions .......................................................................................................................... 9 table 1.3 electrical specifications .................................................................................................................... 10 table 1.4 timing parameters ........................................................................................................................... 18 table 3.1 sbc register map ............................................................................................................................ 28 table 3.2 register irefosc ............................................................................................................................ 35 table 3.3 register ireflposc ........................................................................................................................ 35 table 3.4 register lposctrim ........................................................................................................................... 36 table 3.5 register lposctrimcnt ................................................................................................................. 36 table 3.6 register swrst ................................................................................................................................. 38 table 3.7 register cmdexe ............................................................................................................................... 38 ta ble 3.8 register funcdis ............................................................................................................................ 39 table 3.9 resolution and maximum timeout for prescaler configurations ..................................................... 40 table 3.10 register wdogpresetval ............................................................................................................... 41 table 3.11 register wdogcnt ............................................................................................................................ 41 table 3.12 register wdogcfg ............................................................................................................................ 42 table 3.13 register sleeptadccmp ................................................................................................................. 44 table 3.14 register sleeptcmp ........................................................................................................................ 45 table 3.15 register sleeptcurcnt ................................................................................................................. 45 table 3.16 register irqstat ............................................................................................................................ 48 table 3.17 register irqena ............................................................................................................................... 48 table 3.18 register pwrcfgfp .......................................................................................................................... 61 table 3.19 register pwrcfglp .......................................................................................................................... 62 table 3.20 register gotopd ............................................................................................................................... 63 table 3.21 register disccvtcnt ...................................................................................................................... 63 table 3.22 value for sdmpos2 depending on sdmpos and desired clock delay from sdm to chop clock .... 65 table 3.23 register sdmclkcfglp .................................................................................................................... 68 table 3.24 register sdmclkcfgfp .................................................................................................................... 68 table 3.25 register adccoff ............................................................................................................................ 72 table 3.26 register adccgan ............................................................................................................................ 72 table 3.27 register adcvoff ............................................................................................................................ 72 table 3.28 register adcvgan ............................................................................................................................ 73 table 3.29 register adctoff ............................................................................................................................ 73 table 3.30 register adctgan ............................................................................................................................ 73 table 3.31 register adcpocogain .................................................................................................................... 74 table 3.32 register adccdat ............................................................................................................................ 75 table 3.33 register adcvdat ............................................................................................................................ 75 table 3.34 register adctdat ............................................................................................................................ 75
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 7 april 20, 2016 table 3.35 register adcrdat ............................................................................................................................ 75 table 3.36 register adcgain ............................................................................................................................ 76 table 3.37 register adccrcl ............................................................................................................................ 77 table 3.38 register adccrcv ............................................................................................................................ 77 table 3.39 register adcvrcl ............................................................................................................................ 77 table 3.40 register adcvrcv ............................................................................................................................ 77 table 3.41 register adccrth ............................................................................................................................ 79 table 3.42 register adcctcl ............................................................................................................................ 79 table 3.43 register adcctcv ............................................................................................................................ 79 table 3.44 register adccaccth ........................................................................................................................ 80 table 3.45 register adccaccu .......................................................................................................................... 80 table 3.46 register adcvth ............................................................................................................................... 81 table 3.47 register adcvaccu .......................................................................................................................... 81 table 3.48 register adccmax ............................................................................................................................ 82 table 3.49 register adccmin ............................................................................................................................ 82 table 3.50 register adcvmax ............................................................................................................................ 82 table 3.51 register adcvmin ............................................................................................................................ 82 table 3.52 register adctmax ............................................................................................................................ 83 table 3.53 register adctmin ............................................................................................................................ 83 table 3.54 register adcacmp ............................................................................................................................ 84 table 3.55 register adcgomd ............................................................................................................................ 85 table 3.56 register adcsamp ............................................................................................................................ 85 table 3.57 adcmode settings ............................................................................................................................. 86 table 3.58 register adcctrl ............................................................................................................................ 92 table 3.59 register adcchan ............................................................................................................................ 97 table 3.60 example results of bist .................................................................................................................. 98 table 3.61 register adcdiag ............................................................................................................................ 99 table 3.62 register currentsrcena ............................................................................................................... 99 table 3.63 zssc1750 register lincfg .......................................................................................................... 102 table 3.64 zssc1750 register linshortfilter ........................................................................................ 103 table 3.65 zssc1750 register linshortdelay ........................................................................................... 103 table 3.66 zssc1750 register linwudelay ..................................................................................................... 103 table 3.67 otp memory map .......................................................................................................................... 104 table 3.68 register pullresena .................................................................................................................... 106 table 3.69 register versioncode .................................................................................................................. 106 table 3.70 register pwrtrim .......................................................................................................................... 107 table 3.71 register ibiaslintrim ............................................................................................................... 107 table 4.1 esd protection according to aec - q100 rev. g ........................................................................... 110 table 5.1 zssc1750/51 pins description ...................................................................................................... 112
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 8 april 20, 2016 1 ic characteristics the absolute maximum ratings are stress ratings only. the zssc1750/51 might not function or be operable above the recommended operating conditions. stresses exceeding the absolute maximum ratings might also damage the device. in addition, extended exposure to stresses above the recommended operating conditions might affect device reliability. idt does not recommend designing to the ?absolute maximum ratings.? 1.1 a bsol ute m aximum r atings table 1 . 1 absolute m aximum r atings ( referenced to vsse) no parameter symbol condition s min max unit 1.1.1. external power supply v dde v sse - 0.3 40 v 1.1.2. current sensing , inp pin v inp v sse - 0.3 v dda +0.3 v 1.1.3. current sensing , inn pin v inn v sse - 0.3 v dda +0.3 v 1.1.4. voltage sensing , vbat pin v vbat -18 33 v 1.1.5. voltage sensing , vbat pin v vbat 1h over lifetime -18 40 v 1.1.6. temperature sensing , nth pin v nth v sse - 0.3 v dda +0.3 v 1.1.7. temperature sensing , ntl pin v ntl v sse - 0.3 v dda +0.3 v 1.1.8. lin bus interface , lin pin v lin -16 33 v 1.1.9. lin bus interface , lin pin v lin 1h over lifetime -16 40 v 1.1.10. digital io pins v io v sse - 0.3 v ddp +0.3 v 1.1.11. ambient temperature under bias t a mb 125 c 1.1.12. junction temperature t j 135 c 1.1.13. storage temperature t stor -50 125 c
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 9 april 20, 2016 1.2 r ecommended o perating c onditions table 1 . 2 operating c onditions no. parameter symbol condition s min typ. max unit 1.2.1 operating temperature range t amb ambient temperature ; rth ja =27 k/w -40 115 c 1.2.2 extended temperature range t amb_ext a mbient temperature ; reduced accuracies -40 125 c 1.2.3 supply voltage at bat+ terminal 1) for normal operation v bat + 6 13 18 v 1.2.4 minimum supply voltage at vdde pin : a) when bat+ < 6v, i.e. operation with low battery b) when v bat = v dde , i.e. without using ddde and rdde 1) v dde_low n ormal accuracy for current and temperature measurements r educed accuracy for voltage measurements 4.8 v r educed accuracy for all measurements 4.2 1.2.5 digital input voltage low v il 0 0.3 * v d dp v 1.2.6 digital input voltage high v ih 0.7 * v ddp v ddp v 1) see application diagram on page 2 .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 10 april 20, 2016 1.3 e lectrical p arameters note: s ee important notes at the end of the following table. see section 3.7 for definitions of the ulp and off power states. table 1 . 3 electrical s pecifications no. parameter symbol condition s min typ. max unit supply 1.3.1. average supply current at vdde i dde_avg n ormal m ode (fp s tate, both adcs on) 10 1 2 1 4 ma 1.3.2. average power dissipation p dde_avg n ormal m ode, v dde = 13 v 130 1 56 1 82 mw 1.3.3. current at vdde in sleep mode (ulp s tate with no measurement) i dde_slp t amb = room temperature (rt) 55 a t amb = 115c 100 a 1.3.4. average current at vdde in comparator m ode ( ulp s tate with wake - up interval = 30s and current adc only) i dde_cmp t amb = rt 1 6 0 a 1.3.5. average current at vdde in off state (no measurements ) i dde_ off t amb = rt 50 a 1.3.6. internal analog power supply voltage, vdda pin v dda 2.4 2.5 2.6 v 1.3.7. internal digital power supply voltage, vddl pin v ddl 1.62 1.8 1.98 v external microcontroller ( mcu ) supply 1.3.8. external microcontroller core power supply voltage, vddc pin v ddc default 1. 62 1.8 1.98 v configuration option (see section 2.2 ) 1.08 1.2 1.32 v 1.3.9. external microcontroller power supply voltage (periphery), vddp pin v ddp default 2.97 3.3 3.63 v configuration option (see section 2.2 ) 2.25 2.5 2.75 v 1.3.10. output current of vddp regulator i vddp _out - - 40 ma
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 11 april 20, 2016 no. parameter symbol condition s min typ. max unit 1.3.11. output current capability of vddp pin i vddp see figure 1 . 1 for test circuit - - 30 ma 1.3.12. output current of vddc regulator i vddc_out 40 ma 1.3.13. output current capability of vddc pin i vddc 40 ma digital io pins parameters (vddp = 3.3v) 1.3.14. input low - to - high t hreshold voltage v lh_th 55 60 65 % of v ddp 1.3.15. input h igh - to - l ow threshold voltage v hl_th 35 40 45 % of v ddp 1.3.16. internal p ull - down resistor r pull _down vpin = v ddp 70 190 310 k ? 1.3.17. leakage current i leak _i/o - - 1 a 1.3.18. output l ow level v ol i out = i _i/o - - 20 % of v ddp 1.3.19. output h igh level v oh i out = i _i/o 80 - - % of v ddp 1.3.20. output l ow level of sleepn pin v l_sleepn i sleepn = 0.1ma - - 0.40 v 1.3.21. output h igh level of sleepn pin v h_sleepn i sleepn = 0.1ma 1.40 - - v 1.3.22. pin output current 1) i _i/o mcu_clk pin - - 3.0 ma 1.3.23. all other ios - - 1.5 ma 1.3.24. i sleepn sleepn pin - - 0.1 ma 1.3.25. pin capacitance 1) c _i/o 4.5 5.5 6.5 pf current channel 1.3.26. input signal range 1) range c gain = 4 - 300 300 mv gain = 8 - 150 150 mv gain = 16 - 75 75 mv gain = 32 - 38 38 mv gain = 64 - 19 19 mv gain = 128 - 9.5 9.5 mv gain = 256 - 4.7 4.7 mv gain = 512 - 2.3 2.3 mv 1.3.27. input leakage current 1) i leak_c t amb = 25c - 3 +3 na
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 12 april 20, 2016 no. parameter symbol condition s min typ. max unit 1.3.28. input offset current 1) i offset _c for input signal < 10mv 0.5 1.5 na 1.3.29. conversion rate 1) , 2) rate c programmable 1 16000 hz 1.3.30. oversampling ratio (osr) 1) (sinc 4 decimation filter) osr c programmable 32 256 1.3.31. no missing codes 1) nmc c 18 bits 1.3.32. integral nonlinearity 1) , 3) inl maximum input range 10 60 ppm of fsr 4) 1.3.33. pga gain range 1) a pga 4 512 1.3.34. total gain error 1) err pga_c - 1 1 % 1.3.35. gain drift 1) err_drift pga_c 3 ppm/ c 1.3.36. offset error after calibration 1) v offset_c normal mode chop on, external short (vssa) - 2 2 v low - power state , chop on, external short (vssa) - 0. 6 + 0. 6 v 1.3.37. offset error drift 1) v offset _ drift _ c chop on 2 0 nv/ o c chop off 8 0 nv/ o c 1.3.38. output noise with chop on 1) v noise_c gain = 512, conversion rate = 10hz 1.1 v rms gain = 512, conversion rate = 1khz 1.1 v rms gain = 32, conversion rate = 1khz 3 v rms gain = 4, conversion rate = 1khz 11 v rms
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 13 april 20, 2016 no. parameter symbol condition s min typ. max unit 1.3.39. current offset 1) i bat_offset chop on, gain = 512, r shunt = 100 ? 10 ma 1.3.40. resolution 1) i res chop on, gain = 512, r shunt = 100 ? 1 ma voltage channel 1.3.41. input signal range (at vbat pin) 1) range v resistive divider (1:24) 0 28.8 v 1.3.42. input measurement range 1) range meas_v resistive divider (1:24) 3.6 28.8 v 1.3.43. input valid range for adc 1) range adc_v resistive divider (1:24) 0.15 1.2 v 1.3.44. voltage resistive divider ratio 1) ratio v 24 1.3.45. resistor divider mismatch drift 1) ratio_mis drift_v 3 ppm/ o c 1.3.46. conversion rate 1) , 2) rate v programmable 1 16000 hz 1.3.47. oversampling ratio (sinc 4 decimation filter) 1) osr v programmable 32 256 1.3.48. no missing codes 1) nmc v 18 bits 1.3.49. integral nonlinearity 1) , 3) inl v maximum input range 10 60 ppm of fsr 4) 1.3.50. total gain error 1) (includes resis tor divider mismatch) err pga_v - 0.25 0.25 % 1.3.51. gain drift 1) err_drift pga_v 3 ppm/ c 1.3.52. offset error after calibration: normal mode 1) v offset_v chop on external short (1.25v) 200 v chop off external short (1.25v) 1 mv 1.3.53. offset error drift 1) v offset _ drift _ v chop on 10 v/ c chop off 20 v/ c
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 14 april 20, 2016 no. parameter symbol condition s min typ. max unit 1.3.54. output noise 1) v noise_v chop on gain = 1, conversion rate =10hz 30 50 v rms chop on gain = 1, conversion rate = 1khz 1 v rms temperature channel (external ntc/reference resistor and internal temperature sensor) 1.3.55. voltage drop over ntc resistor 1) v ntc 0 1.2 v 1.3.56. voltage drop over reference resistor 1) v ref_res 0 1.2 v 1.3.57. conversion rate 1) rate t programmable 1 16000 hz 1.3.58. oversampling ratio (sinc 4 decimation filter) 1) osr t programmable 32 256 1.3.59. integral nonlinearity 1) , 3) inl t maximum input range 10 60 ppm of fsr 1.3.60. no missing codes 1) nmc t 16 bit 1.3.61. offset error after zssc1750/51 calibration 1) v offset_t normal mode, chop on, external short (1.25v) - 100 100 v normal mode, chop off, external short (1.25v) - 2 2 mv 1.3.62. offset error drift 1) v offset _ drift _ t chop on 10 v/ o c chop off 20 v/ o c 1.3.63. output noise 1) v noise_t chop on, gain = 1, conversion rate =500hz 50 v rms 1.3.64. resistor to ground at pin ntl 1) gnd res 50 k ? 1.3.65. internal temperature sensor resolution 1) res its - 1/32 - c/lsb 1.3.66. linearity error of internal temperature sensor 1) le its - 2 - c
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 15 april 20, 2016 no. parameter symbol condition s min typ. max unit power - on reset (por) 1.3.67. power - on reset threshold v porb at v dde 2.75 3.0 3.6 v 1.3.68. power - on - reset hysteresis hyst porb at v dde 300 mv 1.3.69. low - voltage flag low_voltage at v dde 1.8 2.0 2.3 v 1.3.70. v ddp high 1) (for vddp = 3.3v configuration) vddp_high at v dde 3.9 4.05 4.2 v 1.3.71. v ddp high hysteresis 1) hyst vddp _high at v dde 400 mv low - power voltage reference 1.3.72. reference bandgap voltage: low - power v bgl 1.16 1.32 v 1.3.73. accuracy (including temperature drift) - 3 3 % 1.3.74. temperature coefficient 1) tc vbgl 50 ppm/k low - power (lp) oscillator 1.3.75. frequency f lpo 125 khz 1.3.76. accuracy (including temperature drift) 1) - 3 3 % high - precision voltage reference 1.3.77. reference bandgap voltage: high - precision v bgh uncalibrated 1.16 1.32 v 1.3.78. temperature coefficient 1) tc vbgh calibrated - 20 5 +20 ppm/k high - precision (hp) oscillator 1.3.79. frequency f hpo 20 mhz 1.3.80. accuracy (including temperature drift) 1) - 1 1 % lin interface 1.3.81. current limitation for driver dominant state 1) i bus_lim lin spec 2.1 param 12 40 200 ma 1.3.82. input leakage current, dominant state, driver off 1) i bus_pas_dom lin spec 2.1 param 13 - 1 ma 1.3.83. input leakage current, recessive state, driver off 1) i bus_pas_rec lin spec 2.1 param 14 20 a
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 16 april 20, 2016 no. parameter symbol condition s min typ. max unit 1.3.84. control unit disconnected from ground 1) i bus_no_gnd lin spec 2.1 param 15 - 1 1 ma 1.3.85. v bat supply disconnected 1) i bus_no_bat lin spec 2.1 param 16 100 a 1.3.86. receiver dominant state, v dde > 7v 1) v busdom lin spec 2.1 param 17 0.4 v dde 1.3.87. receiver recessive state, v dde > 7v 1) v busrec lin spec 2.1 param 18 0.6 v dde 1.3.88. center of receiver threshold 1) v bus_cnt lin spec 2.1 param 19 0.475 0.5 0.525 v dde 1.3.89. receiver hysteresis voltage 1) v hys lin spec 2.1 param 20 0.175 v dde 1.3.90. voltage drop at serial diodes 1) v serdiode lin spec 2.1 param 21 0.4 0.7 1 v 1.3.91. battery shift 1) v shift _bat lin spec 2.1 param 22 0.115 v bat 1.3.92. ground shift 1) v bus_gnd lin spec 2.1 param 23 0.115 v bat 1.3.93. difference between battery shift and ground shift 1) v shift _difference lin spec 2.1 param 24 0 8 % 1.3.94. lin pull - up resistor 1) r slave lin spec 2.1 param 26 20 30 47 k ? 1.3.95. duty cycle 1 1) d1 lin spec 2.1 param 27 0.396 1.3.96. duty cycle 2 1) d2 lin spec 2.1 param 28 0.581 1.3.97. duty cycle 3 1) d3 lin spec 2.1 param 29 0.417 1.3.98. duty cycle 4 1) d4 lin spec 2.1 param 30 0.590 1.3.99. receiver propagation delay 1) t rx _pdr lin spec 2.1 param 31 6 s 1.3.100. symmetry receiver propagation delay, rising/falling edge 1) t rx _sym lin spec 2.1 param 32 - 2 2 s
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 17 april 20, 2016 no. parameter symbol condition s min typ. max unit 1.3.101. capacitance of slave node 1) c slave lin spec 2.1 param 23 250 pf 1.3.102. lin pin capacitance 1) c lin - - 30 pf 1) not tested in production test; given by design and/or characterization. 2) depends on chopping and osr settings. 3) fsr = 1.2v 4) fsr = full - scale input range of the adcs. the input range is given in specification 1.3.26 for current, 1.3 .41 for voltage, and 1.3.55 and 1.3.56 for external temperature . figure 1 . 1 measurement method for determining vddp pin current capability vddp digital ios external mcu vssn vddp zssc1750/51 vss vdd i vddp_out i vddp i io =10ma
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 18 april 20, 2016 1.4 timing p arameters table 1 . 4 timing p arameters no parameter symbol condition s min typ max unit spi protocol t iming (see figure 1 . 2 ) 1.4.1. spi operational frequency 1) f spi - - 8 mhz 1.4.2. s clk c lock period for registers read/write 1) t sclkpreg 125 - - ns 1.4.3. sclk c lock period for otp read 1) t sclkpotp 200 - - ns 1.4.4. sclk c lock pulse width 1) t sclkw 40 50 60 % t sclkp 1.4.5. csn s etup time 1) t csu 50 - - ns 1.4.6. csn h old time 1) t chd 50 - - ns 1.4.7. csn h igh time 1) t chi 300 - - ns 1.4.8. mosi d ata setup time 1) t dsu 20 - - ns 1.4.9. mosi d ata hold time 1) t dhd 10 - - ns 1.4.10. miso d ata access time 1) t dacc - - 25 ns timer 0 (sleep timer) 1.4.11. time interva l 1) slpti1 programmable 0.1 6553.5 s 1.4.12. time interval with post - scaler 1) slpti2 programmable 466 h 1.4.13. resolution 1) slpti1 res 100 ms timer 1 ( watchdog timer wdt ) 1.4.14. time interval 1) wdti programmable 8 6553.5 s 1.4.15. resolution 1) wdti res programmable 0.008 100 ms startup t iming (see figure 1 . 3 ) 1.4.16. porb delay until analog blocks settled 1) t porb_dly 1 ms 1) not tested in production test; given by design and/or characterization.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 19 april 20, 2016 figure 1 . 2 spi protocol timing mosi spi _ clk miso csn 7 ( msb ) 0 ( lsb ) 7 ( msb ) 0 ( lsb ) t sclkp t dacc t dsu t dhd t csu t chd t chi t sclkw
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 20 april 20, 2016 figure 1 . 3 zssc1750/51 power - up and power - down sequence typ vddl v porbmax vddp vdda vddc porb at sto pin t t t t t vdde state t porb_dly off t v porbmin off adc measurements can run off running sbc digital sbc analog mcu running supplied settled supplied off off off
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 21 april 20, 2016 2 circuit description 2.1 overview the zssc1750/51 is a data acquisition system basis chip (sbc) assembled in a p qfn 36 6x6 mm package. it contains a high voltage circuit, analog input stage including peripheral blocks, sigma - delta ( ? ) adcs (sd_adc) , digital filtering, and a lin transceiver (for zssc1750 on ly ) . communication between a n external microcontroller and the sbc is handled by a serial peripheral interface ( spi ) . the functions of the zssc1750/51 are controlled by register settings. the circuit starts after power - on with default register and calibration settings that can be overwritten by the user ?s software. one input channel measures i bat via the voltage drop at the external shunt resistor. the second channel measures v bat and the temperature. by simultaneous ly m easur ing v bat and i bat , it is possible to dynamically determine r di , which is correlated with the state of health (s o h) of the battery. by integrating i bat , it is possible to determine the state of charge (s o c) of the battery. these are the fundamental par ameters for an intelligent battery sensor. the necessary microcontroller and the software for determining these parameters is not part of the zssc1750/51 . figure 2 . 1 functional block d iagram mcu _ clk irq n vddp vddc zssc 1 750 / 51 analog front end sbc common ground pga mux v bat lin vddp _ reg bg _ ref wd _ timer vddc _ reg osc gp _ timer lp _ reg vdda _ reg digital filter config register result register digital filter calibration data path shunt + ? battery sd _ adc sd _ adc r ref ntc lin _ phys ( 1 ) r x d t x d csn sclk miso mosi vdde vdda inp inn vbat nth lin analog block digital block sbc _ pmu mcu _ rstn sleepn irq _ ctrl spi wdt _ dis 1 ) available in zssc 1750 only . nt l during the standby mode and the system ?s s leep m ode ( e.g., engine is off), the system periodically measures the values to monitor the discharge of the battery (see section 3.7 regarding modes) . measurement cycles are controlled by the user?s software and are dependent on the detected events. the zssc1750/51 is designed for low current consumption during sleep mode in the range of less than 60 a.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 22 april 20, 2016 2.2 sbc - to - mcu interface pins the zssc1750/51 connects to the external microcontroller ( mcu ) using pins shown in figure 2 . 2 - a . zssc1750/51 pins c an be classified in three categories: d igi tal ios, microcontroller supply pins , and the p ower state indicator pin . figure 2 . 2 zssc1750/51 digital io interface txd rxd csn sclk mosi miso mcu _ clk vddp mcu _ rstn vddc vddp lin phy spi por & wdt irq ctrl osc 20 mhz vddc wdt _ dis pmu sleepn vssn vddl vssn vssn irqn vssn zssc 1750 / 51 ulp state ? dis core and p eriphery supply for extenal mcu external mcu reset : - power - on reset - watchdog timer ( with ext ernal disable ) optional mcu clock zssc 1750 / 51 irq to external mcu interrupt pin serial peripheral interface to mcu master spi pins to mcu lin uart power mode indicator pin o r disable signal for ext . regulators zssc 1750 / 51 digital ground digio vddp vssn digital out from core c ) structure of zssc 1750 / 51 digital output a ) zssc 1750 / 51 external mcu interface vddp vssn digital input to core b ) structure of zssc 1750 / 51 digital input pull - down enable r pull _ down off state ? dis
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 23 april 20, 2016 2.2.1 digital i / os the digital i/o pins include the spi interface pins, mcu clock, rest and interrupt pins, lin uart pins (for zssc1750 only ), and watchdog timer disable pin. all digital input pins of the zssc1750/51 feature a schmit t trigger (see figure 2 . 2 - b), as well as configurable pull - down resistor s and protection diodes. the pull - down resistors have values specified by parameter 1.3.16 . they are enabled after power - on- reset and c an be further controlled via the pullresena registe r (see s ection 3.11.1.1 ). all digital output pins of the zssc1750/51 have a push - pull stage and protection diodes connected as shown in figure 2 . 2 - c . all digital i / os are supplied by the vddp voltage , which is switched off when the zssc1750/51 is in the ulp or off s tate (see s ection 2.3 ) ; i.e. the i / os are also off in this state. note: in order to avoid parasitic supply of the digital i / o circuitry when the zssc1750/51 is in the ulp or off s tate, the digital outputs of the extern al microcontroller should be disabled. this is valid when the external micro - controller is not supplied by the zssc1750/51. 2.2.2 external microcontroller (mcu) supply pins the zssc1750/51 provides two separate regulators for the external microcontroller supply. the vddp regulato r provides 3. 3v , and vddc provides 1.8v. both voltages are switched off when the zssc1750/51 is in the ulp or off s tate. for more inf ormation regarding the vddp and vddc regulators, including trimming options, refer to sections 3.12.5 and 3.12.6 . the current capability of the vddp and vddc pins is s pecified by parameters 1.3.11 and 1.3.13 respectively. 2.2.3 sleepn power state indicator pin the zssc1750/51 featur es a sleepn pin that indicates the power state of the zssc1750/51 (see section 2.3 ) . when the zssc1750/51 is in the full power (fp) state or low pow er ( lp ) state , the sleepn pin is high ; wh en the state is ulp or off , sleepn is low . in order to remain powered in these states, the sleepn pin circuitry is supplied by the vddl regulator. when high, t h e sleepn pin has a 1.8v output voltage level ; the high and low levels are specified with parameter s 1.3.20 and 1.3.21 . in the application , the sleepn pin can be connected to the external microcontroller (if it remains powered in system s leep m ode), or it can be used for disabling an external circuitry when the zssc1750/51 goes in to one of the power sav ing mode s . depending on the application specifics, an external buffer (e.g. , a transistor) m ight be needed for the sleepn pin for a proper level or current conditioning.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 24 april 20, 2016 2.3 system power states there are four different power states implemented in the zssc1750/51 as illustrated in figure 2.3. full details are given in section 3.7 . figure 2 . 3 zssc175 0/51 power states 6060 off ulp lp fp 2.3.1 full power state ( fp ) the zssc1750/51 enters the full p ower (fp) s tate after power - on reset or after wake - up. in this power state , the zssc1750/51 is fully operational and the external microcontroller is supplied and running (see section 3.7 ) . in the fp state, the adcs are fully powered and running on the 4mhz base clock , which is generated from the 20mhz high - precision oscillator. of the four power states, the fp s tate consumes the most power. the mcu software can trigger the power management unit (pmu) inside the zssc1750/51 to enter any other power state (see section 3.7 ) . 2.3.2 low power state ( lp ) the low power (lp) s tate is intended for scenarios where the zssc1750/51 will only perform low - power measurements without any operation by the external microcontroller (mcu) . fo r its adc operations, it uses a 125khz clock from the low - power oscillator as the base clock. the system can wake up from this power state via any enabled interrupt of the sbc as well as via an mcu reset generated by the w atchdog timer . note: for any sbc interrupt source that will wake up the system, the corresponding interrupt source must be enabled in the sbc. note that the sbc rejects the power - down command when an enabled interrupt source inside the sbc is already activ e. when the system enters the lp s tate from the f p s tate, the microcontroller software must first enable the required interrupt sources for later wake - up in the zssc1750/51 sbc and the microcontroller and it must set the pdstate bit in the pwrcfglp register (see table 3 . 19) followed by a gotopd command (see section 3.7 and table 3 . 20 ) . a rising edge on the csn line triggers the sbc to enter its lp s tate.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 25 april 20, 2016 when any of the enabled interrupts becomes active, the system returns to the fp s tate and continues the software execu tion. note: do not release the csn line by software at the end of sending a power - down command to avoid th e mcu clock being stopped by the sbc at an intermediate state. 2.3.3 ultra low power state ( ulp ) the ultra - l ow power (ulp) state is similar to the lp s tate except that the sbc also disables the power for the external microcontroller . this power state is intended for scenarios where the sbc will only perform low - power measurements without any operation running on the microcontroller . for the zssc1750/51?s adc operations in this state , it uses a 125khz clock from the low - power oscillator as the base clock. the system can wake up from this power state by any enabled interrupt of the sbc. the microcontroller is reset upon wake up by the sbc to guarantee correct st art up. this means that the microcontroller software starts again from address 0 hex after wake up, not at the position where it was stopped. note: for any sbc interrupt source that will wake up the system, the corresponding interrupt source must be enabled in the sbc . note that the sbc rejects the power - down command when an enabled interrupt source inside the sbc is already active. when the system enter s the ulp s tate from the f p s tate, the microcontroller software must first enable the required interrupt sources for later wake - up in the sbc and the microcontroller and it must set the pdstate bit in pwrcfglp register (see table 3 . 19 ) followed by a gotopd command (see section 3.7 and table 3 . 20) . a rising edge on the csn line triggers the sbc to enter its ulp s tate . when any of the enabled interrupts becomes active, the system returns to f p s tate and restarts the microcontroller software execution. note: do not release the csn line by software at the end of sending a power - down command to avoid the microcontroller clock being stopped by the sbc at an intermediate state. 2.3.4 off power state the off power state has the lowest power consumption : no measurements can be performed as all oscillators are stopped. this power state i s intended for scenarios where no measurement s will be performed and the system will consume as l ittle power as possible. the system can wake up from this power state only by receiving a wakeup frame over the lin interface ( only for the zssc1750) or after a power - on reset (for zssc1750/51) . the exter nal microcontroller is reset at wake up by the sbc to guarantee correct start up. this means that the microcontroller?s software starts again from address 0 hex after wake up, not at the position where it was stopped. note: for any sbc interrupt source that will wake up the system, the corresponding interrupt source , e.g. the lin wakeup interrupt (for the zssc1750 only), must be enabled inside the sbc. note that the sbc rejects the power - down command when an enabled interrupt source in the sbc is already act ive. when the system enters the off power state from the fp s tate, the microcontroller software must first enable the required interrupt source in the sbc , e.g. the lin interrupt (for the zssc1750 only ) , and the microcontroller and must set the pdstate bit in register pwrcfglp (see table 3 . 19 ) followed by a gotopd command (see table 3 . 20) . a rising edge on the csn line triggers the sbc to enter its off s tate. when any of the enabled interrupts becomes active, the zssc1750/51 returns to the fp state and the external microproce ssor can restart its software execution . note: do not release the csn line by software at the end of sending a power - down command to avoid the mcu clock being stopped by the sbc at an intermediate state.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 26 april 20, 2016 3 zssc1750/51 functional block descriptions 3.1 serial peripheral interface (spi slave ) the zssc1750/51 is fully controllable by an external microcontroller via an integrated four - wire spi slave . it only operates in a single mode whe n both the clock polarity and the clock phase are 1 ( the clock is high when in active, data is sent on the falling spi clock edge , and data is sampled on the rising spi clock edge). the accessible registers of the sbc as well as the one- time programmable ( otp ) memory can be read via the spi. the i nternal status information of the sbc is also shifted - out during the address and length bytes of the implemented spi protocol (see figure 3 . 1 ) . read and write burst accesses of up to 128 bytes are supported. the spi chip - select line csn must be low during any transfer until the complete transfer has finished. this is needed as the csn input is not only used as an enable signal but also as a n asynchronous reset for part of the spi front - end . the reason for this is to be able to set the spi back to a defined state via the microcontroller as well as to extract status information without needing to access any register. the csn input can be kept low between two transfers. the csn input must only be driven high for execution of the ?go - to - power - down? command after the required register settings have been completed . note: a high level at csn resets the internal spi state machine. 3.1.1 spi protocol the spi slave module only operat es with a clock polarit y of 1 ( sclk is high when no transfer is active) and with a clock phase of 1 (data is sent on the falling edge ; data is sampled on the rising edge). for any access, the csn input must be low. at the end of any read access, the csn input can be kept low. fo r write accesses that change the power state , the csn input must be driven high at the end of the write access ; it can be kept low for write accesses to other registers. during a n spi access, the csn input must be kept low. important : driving the csn input high during a read transfer can cause a loss of data. in each spi transfer , 1 to 128 bytes can be read or written in one burst access. all bytes are sent and received with the msb first. as shown in figure 3 . 1 , each spi transfer starts with two bytes sent by the master while the slave sends back status information in parallel. the first of the two bytes sent by the master is the address byte containing the first address to be accessed. when multiple bytes are read or written, the received spi address is internally incremented for each data byte. the second byte starts with the access type of the transfer (1 = write; 0 = read) followed by the 7 - bit lengt h field indicating the number of data bytes that will be read or written. the exception is the length value of 0 , which is interpreted by the slave spi as 128 bytes. the status information sent back by the slave during the address and length bytes starts w ith a fixed value of a hex . this can be used to detect whether the connection is still present. the next bits sent are the s lave s tatus w ord (ssw), which is 12 bits of actual status information. the 12 ssw bits have the following definitions : ssw[11]: v alue of the low - voltage flag ssw[10:8]: r eset status ssw[7]: w atchdog active flag ssw[6]: l ow - power oscillator trimming circuit activ e ssw[5]: v oltage/temperature adc active
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 27 april 20, 2016 ssw[4]: c urrent adc active ssw[3]: lin short protection active (applicable for zss c1750 only) ssw[2]: lin txd timeout protection active (applicable for zssc1750 only) ssw[1]: r eadable sleep timer value valid ssw[0]: otp download proced ure active note: after the external microcontroller has been reset, t he user?s s oftware can read the low - voltage flag and the reset status by a single - byte transfer ( important: send only the address byte ) to shorten the initialization phase (e.g. , when a reset was caused by a wake - up event) without needing to read or write further bytes including the leng th byte. after the address byte and length byte are sent by the master, either the master (write transfer) or the slave (read transfer) is transmitting data. the slave ignores all incoming bits while it is sending the requested number of data bytes (read ) , and the data bytes returned during a write transfer have no meaning. figure 3 . 1 show s a read and a write burst access to the sbc . figure 3 . 1 read and write burst access to the sbc read access sclk csn mosi miso a [7:0] l[6:0] r ssw[11:0] d 0 [7:0] d l-1 [7:0] write access sclk csn mosi miso a[7:0] l[6:0] w ssw[11:0] d 0 [7:0] d l-1 [7:0] a: start address of spi access r: read access (msb of second byte is low) w: write access (msb of second byte is high) l: number of data bytes (0 = 128 bytes) ssw: slave status word sclk: spi clock
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 28 april 20, 2016 3.2 sbc register map (result register block and config register block) table 3 . 1 defines the registers in the sbc. in the ?access? column, the following abbreviations indicate the read/write status of the register s : rc = read - clear; ro = read - only; rw = readable and writa ble; wo = write - only; w1c = write - one - to - clear , rws = read - write - set . for more details, see the subsequent sections for the individual registers in section 3 . important: there is a distinction between ?unused? and ?reserved? addresses. no problem occurs when writing to unused addresses , but writing 0 hex to unused addresses for future expansions i s recommended. reserved addresses must always be written with the given default value. table 3 . 1 sbc register map name address order default access short description irqstat 00 hex lsb 00 hex rc i nterrupt status register 01 hex msb 00 hex rc adccdat 02 hex lsb 00 hex ro adc result register of a single current measurement 03 hex --- 00 hex ro 04 hex msb 00 hex ro adcvdat 05 hex lsb 00 hex ro adc result register of a single voltage measurement 06 hex --- 00 hex ro 07 hex msb 00 hex ro adcrdat 08 hex lsb 00 hex ro adc result register of a single temperature measurement by reading a voltage across the reference resistor (external temperature measurement only) 09 hex msb 00 hex ro adctdat 0a hex lsb 00 hex ro adc result register of a single temperature m easurement by reading a voltage across the ntc resistor (external temperature measurement) or of a differential voltage (vptat ? vbgh; internal temperature measurement) 0b hex msb 00 hex ro adccaccu 0c hex lsb 00 hex ro a ccumulator register for current measurements 0d hex --- 00 hex ro 0e hex --- 00 hex ro 0f hex msb 00 hex ro adcvaccu 10 hex lsb 00 hex ro a ccumulator register for voltage measurements 11 hex --- 00 hex ro 12 hex msb 00 hex ro adccmax 13 hex lsb 00 hex ro m aximum current value measured in configured measurement sequence 14 hex msb 80 hex ro adccmin 15 hex lsb ff hex ro m inimum current value measured in configured measurement sequence 16 hex msb 7f hex ro
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 29 april 20, 2016 name address order default access short description adcvmax 17 hex lsb 00 hex ro m aximum voltage value measured in configured measurement sequence 18 hex msb 80 hex ro adcvmin 19 hex lsb ff hex ro m inimum voltage value measured in configured measurement sequence 1a hex msb 7f hex ro adccrcv 1b hex lsb 00 hex ro c ounter register containing the number of current measurements 1c hex msb 00 hex ro adcctcv 1d hex --- 00 hex ro counter register containing the number of current measurements greater than or equal to the threshold adcvrcv 1e hex --- 00 hex ro c ounter register containing the number of voltage measurements unused 1f hex --- 00 hex --- --- sleeptcurcnt 20 hex lsb 00 hex ro c urrent sleep timer value 21 hex msb 00 hex ro u nused 22 hex to 2f hex --- 00 hex --- --- adccgan 30 hex lsb 00 hex rw d igital gain correction for current channel 31 hex --- 00 hex rw 32 hex msb 80 hex rw adccoff 33 hex lsb 00 hex rw d igital offset correction for current channel 34 hex --- 00 hex rw 35 hex msb 00 hex rw adcvgan 36 hex lsb 00 hex rw d igital gain correction for voltage channel 37 hex --- 00 hex rw 38 hex msb 80 hex rw adcvoff 39 hex lsb 00 hex rw d igital offset correction for voltage channel 3a hex --- 00 hex rw 3b hex msb 00 hex rw adctgan 3c hex lsb 00 hex rw d igital gain correction for temperature channel 3d hex msb 80 hex rw adctoff 3e hex lsb 00 hex rw d igital offset correction for temperature channel 3f hex msb 00 hex rw adccrcl 40 hex lsb 00 hex rw n umber of current measurements before the ready strobe is generated 41 hex msb 00 hex rw
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 30 april 20, 2016 name address order default access short description adccrth 42 hex lsb 00 hex rw a bsolute current value is compared to this threshold in c urrent t hreshold c omparator m ode 43 hex msb 00 hex rw adcctcl 44 hex --- 00 hex rw n umber of current measurements greater than or equal to the threshold before the set interrupt strobe is generated adcvrcl 45 hex --- 00 hex rw n umber of voltage measurements before ready strobe is generated adcvth 46 hex lsb 00 hex rw v oltage threshold level for t hreshold c omparator (unsigned) or a ccumulator (signed) m odes 47 hex msb 00 hex rw adccaccth 48 hex lsb 00 hex rw a ccumulator threshold for current channel 49 hex --- 00 hex rw 4a hex --- 00 hex rw 4b hex msb 00 hex rw adctmax 4c hex --- 00 hex rw u pper threshold for temperature measurement adctmin 4d hex --- 00 hex rw l ower threshold for temperature measurement adcacmp 4e hex lsb 30 hex rw adc function enable register 4f hex msb 00 hex rw adcgomd 50 hex --- 1 0 hex rw r eference voltage and sigma - delta modulator (sdm) configuration (see section 3.8 ) adcsamp 51 hex --- 00 hex rw o versampling and filter configuration adcgain 52 hex --- 00 hex rw gain configuration register for analog amplifiers pwrcfgfp 53 hex --- 00 hex rw p ower configuration register for f ull p ower (fp) s tate irqena 54 hex lsb 00 hex rw i nterrupt enable register 55 hex msb 00 hex rw adcctrl 56 hex --- 00 hex rw adc control register for full power state (fp) adcpocogain 57 hex --- 00 hex rw p ost - correction gain configuration unused 58 hex - 5e hex --- 00 hex --- --- disccvtcnt 5f hex --- 00 hex rw c onfiguration register for some power - down states sleeptadccmp 60 hex lsb 00 hex rw c ompare value for adc trigger timer 61 hex msb 00 hex rw sleeptcmp 62 hex lsb 00 hex rw c ompare value for sleep timer 63 hex msb 00 hex rw pwrcfglp 64 hex --- 20 hex rw p ower configuration register for power - down state s
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 31 april 20, 2016 name address order default access short description gotopd 65 hex --- 00 hex wo p ower - down activation register unused 66 hex to 67 hex --- 00 hex --- --- cmdexe 68 hex --- 02 hex wo/rw c ommand execution register unused 69 hex to 6f hex --- 00 hex --- --- wdogcnt 70 hex lsb ff hex ro c urrent watchdog counter value 71 hex msb ff hex ro wdogpresetval 72 hex lsb ff hex rw p reset value for watchdog counter 73 hex msb ff hex rw wdogcfg 74 hex --- 09 hex rw c onfiguration register for watchdog counter unused 75 hex to 77 hex --- 00 hex --- --- lposctrimcnt 78 hex lsb 00 hex ro r esult counter of low - power oscillator trim circuit 79 hex msb 00 hex ro ireflposc 7a hex --- 52 hex rw t rim value for low - power oscillator lposctrim 7b hex --- 04 hex rw c onfiguration register for trim circuit of lp oscillator unused 7c hex to 7f hex --- 00 hex --- --- swrst 80 hex --- 0 0 hex wo s oftware reset unused 81 hex to af hex --- 00 hex --- --- sdmclkcfglp b0 hex lsb 18 hex rw c lock configuration for sdm clock in power - down state b1 hex msb 00 hex rw sdmclkcfgfp b2 hex lsb 08 hex rw c lock configuration for sdm clock in full - power state (fp) b3 hex msb 90 hex rw lincfg b4 hex --- 00 hex rw/w1c zssc1750: configuration for lin control logic zssc1751: not used important: must remain as default for zssc1751 linshortfilter b5 hex --- 0f hex rw zssc1750: configuration for lin short de - bounce filter zssc1751: not used important: must remain as default for zssc1751 linshortdelay b6 hex --- 4f hex rw zssc1750: configuration for lin short tx - rx delay zssc1751: not used important: must remain as default for zssc1751
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 32 april 20, 2016 name address order default access short description linwudelay b7 hex --- 14 hex rw zssc1750: configuration for lin wake - up time zssc1751: not used important: must remain as default for zssc1751 pullresena b8 hex --- ff hex rw c onfiguration register for pull - down resistors funcdis b9 hex --- 00 hex rw d isable bits for dedicated functions versioncode ba hex lsb 0 1 hex ro v ersion code bb hex msb 0 3 hex ro u nused bc hex - bf hex --- 00 hex --- --- pwrtrim c0 hex --- 7c hex rw t rim bits for voltage regulators and bandgap irefosc c1 hex lsb 10 hex rw t rim values for high - precision oscillator c2 hex msb 4 0 hex rw ibiaslintrim c3 hex --- 10 hex rw zssc1750: bias current trim register for lin block zssc1751: not used important: must remain as default for zssc1751 r eserved c4 hex --- 00 hex rw --- reserved c5 hex --- 00 hex rw --- reserved c6 hex --- 00 hex rw --- reserved c7 hex --- 00 hex rw --- reserved c8 hex --- 00 hex rw --- reserved c9 hex --- 00 hex rw --- reserved ca hex --- 0 8 hex rw --- reserved cb hex --- 00 hex rw --- reserved cc hex --- 00 hex rw --- reserved cd hex --- 00 hex rw --- reserved ce hex --- 00 hex rw --- reserved cf hex --- 00 hex rw --- adcchan d0 hex --- 00 hex rw a nalog multiplexer configura tion during test / diagnosis adcdiag d1 hex --- 80 hex rw e nable register for test/ diagnosis currentsrcena d2 hex --- 00 hex rw enable register for current sources reserved d3 hex --- 00 hex rw --- reserved d4 hex --- 00 hex rw --- reserved d5 hex --- 00 hex rw ---
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 33 april 20, 2016 name address order default access short description reserved d6 hex --- 00 hex rw --- reserved d7 hex --- 00 hex rw --- reserved d8 hex --- 00 hex rw --- reserved d9 hex --- 00 hex rw --- reserved da hex --- b8 hex rw --- reserved db hex --- 00 hex rw --- reserved dc hex --- 00 hex rw --- reserved dd hex --- 00 hex rw --- reserved de hex --- 00 hex rw --- reserved df hex --- 00 hex rw --- otp e0 hex to ff hex --- --- ro otp raw data (s ee section 3.10 .) 3.3 zssc1750/51 clock and reset logic 3.3.1 clock sources the zssc1750 /51 sbc contains two different oscillators, a low - power oscillator (lp oscillator) pro viding a clock of 125 khz (typical) with an accuracy of 3% and a high - precision oscillator (hp oscillator) providing a clock of 20mhz (typical) with an accuracy of 1%. the low - power oscillator is always active except in the off s tate while the high - precision oscillator is only active in fu ll- power state (fp) . t he clock from the high - precision oscillator is routed to the external microcontroller via the mcu_clk pin . th ere are th ree different internal clocks generated from the two clocks from the oscillators for the digital core of the sbc : ? l ow - power clock (lpclk): this clock is directly driven by the low - power oscillator and has a frequency of 125khz. it is used for the watchdog timer, the sleep timer , and the power management unit. ? divided clock (divclk): this clock is derived from the high - precision oscillator and has a frequency of 4 mhz . it is used for the register file, the low - power oscillator trimming circuit, the lin support logic (zssc7150 only) , and the otp controller. ? multiplexed clock (muxclk): t his clock is identical to the divclk in the full - power state (fp) and identical to lpclk in the lp and ulp s tate s . it is used for the adc controller unit and the interrupt controller. both oscillators are trimmed during the production test , and the trim values are stored in the otp memory ( iref_osc_0, iref_osc_1, iref_osc_2, iref_osc_3, iref_lp_osc; see table 3 . 67 ). the high precision os cillator is routed to the mcu_clk pin, which can be used as a clock source for the external microcontroller or other digital devices, so it is important that the clock from the high - precision oscillator has the correct frequency. therefore , the two trimmin g values for the high - precision oscillator are protected by redundancy inside the otp. software can check the validity of the trim values and the redundancy bits by reading the otp raw data directly from the otp via the spi .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 34 april 20, 2016 note: the trimming values for b oth oscillators should also be stored by the user?s external microcontroller so that the user?s software is able to check the validity of the trimming values. on detection of errors inside the otp, the user?s software can write the correct values via spi. 3.3.2 trimming the low - power oscillator because the clock from the low - power oscillator is less accurate than the clock from the high - precision oscillator, a trimming circuit is implemented that trims the low - power oscillator using the divided clock divclk. ther e are two options for trimming the low - power oscillator. one option is to allow the hardware to update the trim value for the low - power oscillator automatically so that no user interference is necessary. for this, the user only needs to set the lposctrimena and lposctrimupd bit s in register lposctrim to 1 as well as setting the lposctrimcfg field as needed (see table 3 . 4 ) . the latter configuration value defines how many low - power clock periods are used for frequency calculation. while the trimming circuit is faster when fewer periods are used, the result of the frequency calculation is more accurate when more periods are used. in the first part of the tri mming loop, the circuit determines the frequency of the low - power oscillator. when the measured frequency is too low, the hardware increments the trim value by 1 ; if it is too high, the hardware decrements the trim value by 1. otherwise , the trim value rem ains unchanged. after changing the trim value, the hardware measures the (new) frequency. this algorithm is only stopped when the user?s software clears the lposctrimena bit (trimming logic stops after a final update) or when any low - power state is entered. the second option is to use the trim circuit only to measure the frequency but to update the trim value via the user?s software. this can be preferable when the target frequency is not equal to 125 khz. for this, the user only needs to set the lposctrimena bit to 1 and set the lposctrimupd bit to 0 as well as setting the lposctrimcfg field as needed. next , the user must clear the lposctrimena bit without changing the oth er values in the register and must wait until the hardware has finished to calculate the frequency (wait until ssw[6] is 0). by reading the lposctrimcnt register , the user can calculate the actual frequency of the low - power oscillator using the follo wing f ormula: mhz 4 f 2 1 f f hp 2 fg lposctrimc hp lp = ? + = + nt l posctr i mc ( 1 ) after determin ing the actual frequency, the user can change the trim value for the low - power oscillator lposctrimval as required (see table 3 . 3 ) and re - enable the trimming circuit to check the new frequency. note: the trimming circuit can be kept active when going to any low - power state. the pmu interrupts the trimming circuit on tra nsition to the low - power state and restarts it after wakeup. this is needed as divclk is stopped in any low - power state.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 35 april 20, 2016 3.3.3 clock trimming and configuration registers 3.3.3.1 register ?irefosc? ? trim values for the high - p recision oscillator table 3 . 2 register irefosc name address bits default access description ireftcosctrim c1 hex [4:0] 10 000 bin rw trim value to minimize the temperature coefficient of the high - precision oscillator. note: this value is automatically updated by the otp controller after an sbc reset. u nused [6:5] 0 0 bin ro u nused; always write as 0 . irefosctrim[0] [7] 0 bin rw trim value for the high - precision oscillator. the frequency of the high - precision oscillator increases (decreases) when this value is incremented (decremented). note: this value is automatically updated by the otp controller after an sbc reset. irefosctrim[8:1] c2 hex [7:0] 4 0 hex rw 3.3.3.2 register ?irefl posc? ? trim value for the low - p ower oscillator table 3 . 3 register ireflposc name address bits default access description lposctrimval 7a hex [6:0] 1010010 bin rw trim value for the low - power oscillator. the frequency of the low - power oscillator increases (decreases) when this value is incremented (decremented). note: this value is automatically updated by the otp controller after sbc reset. u nused [7] 0 bin ro u nused; always write as 0 .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 36 april 20, 2016 3.3.3.3 register ?lposctrim? ? configuration register for the low - power oscillator trimming circuit table 3 . 4 register lposctrim name address bits default access description lposctrimena 7b hex [0] 0 bin rw if set to 1, enables the low - power oscillator trimming circuit. note: when the user disables the trimming feature, the trimming logic continues its operation until it has finished the current calculation and then stops. the user can check that the trimming circuit has stopped by evaluating ssw[6] , which is 0 when the trimming circuit is inactive . lposctrimupd [1] 0 bin rw update bit for the low - power oscillator trimming circuit. when set to 1, the trimming circuit is allowed to update lposctrimval in register ireflposc . when set to 0, no hardware update is performed. note: do not change while trimming circuit is active. lposctrimcfg [3:2] 0 1 bin rw this value selects the number of clock periods of the low - power oscillator to be used to determine the frequency. 0 4 clock periods 1 8 clock periods 2 16 clock periods 3 32 clock periods note: do not change while trimming circuit is active. u nused [7:3] 0 0000 bin ro u nused; always write as 0 . 3.3.3.4 register ?lposctrimcnt? ? result counter of the low - p ower oscillator trimming circuit table 3 . 5 register lposctrimcnt name address bits default access description lposctrimcnt[7:0] 78 hex [7:0] 0 0 hex ro result counter of the low - power oscillator trimming circuit. this value will only be read when t he t rimming circuit is inactive (ssw[6] == 0). lposctrimcnt[10:8] 79 hex [2:0] 0 00 bin ro u nused [7:3] 0 0000 bin ro u nused; always write as 0
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 37 april 20, 2016 3.3.4 reset s the main reset source is the integrated power - on- reset circuit , which resets the complete digital core of the sbc when vdde drops below 3.0v (typical). there are three other reset sources that reset the complete digital core of the sbc except the watchdog timer and its configuration registers. these additional reset source s are ? watchdog reset: this reset occurs when the active watchdog timer expires without being handled by the user?s software. ? software reset: this reset can be generated by the user by writing the value a9 hex to register swrst. ? pmu error reset: this reset occurs if the power management unit (pmu) goes into an invalid state (e.g. , due to cosmic radiation ) . if any of these four reset s occurs, the power - on procedure is executed , which powers up the required analog blocks and starts the download pr ocedure for the otp. this download procedure transfers the otp content s into the appropriate registers if the otp content is valid. t he mcu_rstn pin is driven low, which can be used to reset the connected external microcontroller . the microcontroller reset is released after the power - up procedure has finished. the mcu_rstn pin is also driven low when the system goes to off or ulp s tate because the power suppl ies to the microcontroller (vddp, vddc) are disabled in these power - down st ates. in this case, the mcu_rstn low state is released after a wake - u p event has occurred and the power supplies to the external microcontroller have stabilized. another possible reset source for the external microcontroller is vddpreset , which is also generated by the power - on- reset circuit when vdde drop s below 4.05v (typical). in this case, it can not be guaranteed that vddp , which is needed for correct operation of the external microcontroller , is still valid if vddp is trimmed to the higher level of 3.3v (see section 3.12.5 ) . the digital core of the sbc observes the input from the power - on - reset block and generates the mcu_rstn signal only when all of the following conditions are true: ? vddp is trimmed to 3.3v (bit vddptrim of register pwrtrim is set to 1) . ? the zssc1750/51 system is in the full - power state (fp) . ? vddp reset is not disabled (bit disvddprst of register funcdis is set to 0 ; see table 3 . 8 ) . 3.3.4.1 the reset status the external microcontroller can easily check the rea son for being reset by a single - byte transfer to the sbc (spi address byte only) and evaluating ssw[10:8], which contains the reason for the last reset (reset status). this value can be evaluated by the user?s software for different actions after reset: reset status 0: in this case , the reset was generated by t he power - on - reset cell. the sbc was reset , and a mcu_rstn signal was generated to reset the external microcontroller . reset status 1: the watchdog timer was not handled and has expired (see section 3.4 ) . the sbc logic (except the watchdog timer and its configuration registers) was reset and a mcu_rstn signal was generated to reset the external microcontroller reset status 2: only a mcu_rstn signal was generated to reset the external microcontroller due to a wakeup from the ulp or off s tate.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 38 april 20, 2016 reset status 3: the user?s software has forced a reset. the sbc logic (except the watchdog timer and its configuration registers) was reset and a mcu_rstn signal was generated to reset the external microcontroller . reset status 4: vddp has dropped below 3.3v , and the external microcontroller was active. only a mcu_rstn signal was generated to reset the external microcontroller . reset status 5: th e pmu is in an illegal state. the sbc logic was reset ( except the watchdog timer and its configuration registers ) and a mcu_rstn signal was generated to reset the external microcontroller . 3.3.4.2 the low - v oltage flag the low - voltage flag is part of the analog blo ck. the low - voltage flag is at low - level state a fter power - on- reset. it can be set by the user?s software by writing the value ?1? to bit lvfset in register cmdexe . it is cleared by the power - on- reset cell when vdde drops below 1.9v (typical) . when vdde drops below this threshold, it cannot be guaranteed that the vddl voltage is high enough to provide a reliable sbc digital supply . the low - voltage flag is mapped to spi ssw[11] where the user?s software can read its value. 3.3.4.3 register ?swrst? ? software reset table 3 . 6 register swrst name address bits default access description swrst 80 hex [7:0] 0 0 hex wo writing a9 hex to this register forces a software reset , which generates a mcu_rstn signal to reset the external microcontroller as well as the sbc digital core except the watchdog timer and its configuration registers. always read s as 0. 3.3.4.4 register ?cmdexe? ? triggering command execution by software table 3 . 7 register cmdexe name address bits default access description wdogclr 68 hex [0] 0 bin rw writing 1 to this bit clears the watchdog timer. this bit is cleared by hardware after the watchdog is cleared. as long as the clear procedure is active, any further writes to this bit are rejected. otpdownload [1] 1 bin wo s trobe register; write 1 to start the download procedure from the otp; always read s as 0 . lvfset [2] 0 bin wo s trobe register; write 1 to set the low - voltage flag; always reads as 0. unused [7:3] 0 0000 bin ro u nused; always write as 0 .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 39 april 20, 2016 3.3.4.5 register ?funcdis? ? disabling vddp reset and sto output pin table 3 . 8 register funcdis name address bits default access description disvddprst b9 hex [0] 0 bin rw w hen set to 1, vddpreset does not generate a mcu_rstn signal to reset the external microcontroller . disstoout [1] 0 bin rw w hen set to 1, the output driver of the sto pin is disabled . unused [7:2] 0 00000 bin ro unused; always write as 0. 3.4 sbc watchdog timer (wd_timer block) the sbc contains a configurable watchdog timer (down counter) for the zssc1750/51 when it is running using the clock from the low - power oscillator. it is used to recover from an invalid software or hardware state. to avoid a reset of the system, the watchdog must be periodically serv iced . the only part of the system that will not be reset by the watchdog reset is the watchdog itself and its configuration registers. figure 3 . 2 structure of the w atchdog t imer configurable prescaler 1 : 1 1 : 125 1 : 1250 1 : 12500 lpclk (125 khz) 16-bit down counter wdogprescalecfg (register file) == 0? & set wdogcnt (register file) wdirq (irq ctrl) wdogirqfuncena (register file) wdrst (rstctrl) & set o r by default, the watchdog timer is active starting with a counter value of ffff hex and a prescaler of 125. this is done to guarantee that the boot code of the external microcontroller has enough time to finish. during the initialization phase of the system, the user?s software can disable, reconfigure , and restart the watchdog. disablin g the watchdog before configuration is required as all write accesses to the register wdogpresetval and the register wdogcfg except the bits wdoglock and wdogena (see table 3 . 12) are blocked when the watchdog is active. as it takes multiple low - power clock cycles until the enable signal is evaluated inside the watchdog clock domain, the ssw[7] bit ( wdactive ) must be checked to determine if write accesses are possible. to avoid any malfunction during reconfiguration, the prescaler registers are set to 0 and the counter register is set to ffff hex at disable.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 40 april 20, 2016 when the watchdog is disabled, configuration is possible. the register wdogpresetval contains the va lue that will be copied into the down counter in the first enable cycle or when the watchdog timer is serv iced via the wdogclr bit in register cmdexe . the field wdogprescalecfg in register wdogcfg configures the prescaler. the resolution and maximum timeou t for the watchdog depend on the configuration as shown in table 3 . 9 . table 3 . 9 resolution and maximum timeout for prescaler configurations wdogprescalecfg setting prescaler configuration resolution maximum timeout 0 1:1 8 s 524 ms 1 1:125 1 ms 65.5 s 2 1:1250 10ms 655.3 s 3 1:12500 100ms 6553.5 s as the maximum timeout value might still be too small for some application s , the user can use the wdogpmdis bit in register wdogcfg to select whether the watchdog timer will be halted during any power - down state (bit set to 1) or not (bit set to 0). it is also possible to use the watchdog timer (wdt) as a wak e - up source. when the wdogirqfuncena bit in register wdogcfg is set to 1 and the down counter reaches 0, an interrupt is generated ( instead of a reset that would wake up the system ) and the down counter reloads the preset value and continues its operation. when the watchdog timer expires for a second time without service, the watchdog reset is generated. if the wdogirqfuncena bit is set to 0, the reset is already generated when the t imer expires for the first time. after reconfiguration, the watchdog timer is re - enabled. to avoid further (accidental) changes to the watchdog timer configuration registers, the user can set the wdoglock bit inside the register wdogcfg to 1. if this bit i s set , all write accesses are blocked. the wdoglock bit will only be cleared by a power - on reset. the wdt can also be disabled by driving the wdt_dis pin high . in this case it is halted, but still can be cleared via the wdogclr bit in register cmdexe (see table 3 . 7 ). this functionality is useful in the external microcontroller?s in - circuit programming mode to disable a reset generated by the watchdog timer. to perform the required period servicing of the watchdog timer , the user must write the value 1 to the wdogclr bit in register cmdexe . to avoid any malfunction if the watchdog is serv iced too often, any consecutive write accesses to the wdogclr bit are blocked until the first clear process has finished. important : the preset value programmed to the wdogpresetval register must never be 0 hex as this would immediately cause a reset forcing the system into a dead lock . it is strongly recommended that the user?s software checks the programmed reload value before re - enabling the watchdog. important : the preset value must not be too small. the u ser must take into account critical system timings including power - up times and flash programming/erasing times. note: the reconfiguration of the registers wdogpresetval and wdogcfg, including bits wdogena and wdoglock, can be done in a single spi burst write access.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 41 april 20, 2016 3.4.1 watchdog registers 3.4.1.1 register ?wdogpresetval? ? preset value for the watchdog timer table 3 . 10 register wdogpresetval important: the preset value programmed to this register must never be 0 hex (see section 3.4 above). name address bits default access description wdogpresetval[7:0] 72 hex [7:0] ff hex rw lower byte of the preset value of the watchdog timer. this value is loaded into the lower byte of the watchdog counter when the watchdog is enabled or when the watchdog is cleared. note: t his bit can only be written when the watchdog is not locked ( wdoglock == 0) and when t he watchd og is inactive ( ssw[7] == 0). wdogpresetval[15:8] 73 hex [7:0] ff hex rw upper byte of the preset value of the watchdog timer. this value is loaded into the upper byte of the watchdog counter when the watchdog is enabled or when the watchdog is cleared. note: t his bit can only be written when the watchdog is not locked ( wdoglock == 0) and when the watchdog is inactive ( ssw[7] == 0). 3.4.1.2 register ?wdogcnt? ? current value of watchdog timer table 3 . 11 register wdogcnt name address bits default access description wdogcnt[7:0] 70 hex [7:0] 0 0 hex ro lower byte of current watchdog timer value wdogcnt[15:8] 71 hex [7:0] 0 0 hex ro upper byte of current watchdog timer value
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 42 april 20, 2016 3.4.1.3 register ?wdogcfg? ? watchdog timer configuration register table 3 . 12 register wdogcfg name address bits default access description wdogena 74 hex [0] 1 bin rw global enable bit for the watchdog timer. note: t his bit can only be written when the watchdog is not locked ( wdoglock == 0). wdogpmdis [1] 0 bin rw when this bit is set to 1, pmu stops the watchdog during any power - down state. note: t his bit can only be written when the watchdog is not locked ( wdoglock == 0). wdogirqfuncena [2] 0 bin rw when this bit is set to 1, the watchdog reloads the preset value when expiring for the first time and generates an interrupt instead of a reset. a reset will always be generated when the watchdog timer expires for the second time. note: t his bit can only b e written when the watchdog is not locked ( wdoglock == 0) and when the watchdog is inactive ( ssw[7] == 0) wdogprescalecfg [4:3] 0 1 bin rw p rescaler configuration : 0 no prescaler active 1 prescaler of 125 is active 2 prescaler of 1250 is active 3 prescaler of 12500 is active note: t his bit can only be written when the watch - dog is not locked ( wdoglock == 0) and when the watchdog is inactive ( ssw[7] == 0) u nused [6:5] 0 0 bin ro u nused; always write as 0 . wdoglock 7 0 bin rws when this bit is set to 1, all write accesses to the other bits of this register as well as to the wdogpresetval registers are ignored. this bit can only be written to 1 and is only cleared by a power - on reset.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 43 april 20, 2016 3.5 sbc sleep timer (gp_timer block) the integrated sleep timer (up counter) in the gp_timer (general - purpose timer) block is only active when the system is in any low - power state and it is runnin g with the 125 khz clock from the low - power oscillator. the sleep timer consists of three blocks: ? a fixed prescaler that divides the incoming 125 khz clock from the low - power oscillator by 12500 to get a timer resolution of 10 hz. ? a 16 - bit counter that generates an interrupt (signal: stlrq) when the timer reaches the programmed compare value in the sle eptcmp register (see table 3 . 14). ? a 12 - bit counter that triggers the pmu (with signal stadctrigger) when the timer reaches the programmed compare value in the sleeptadccmp register (see table 3 . 13 ) to power - up the adc blocks and to perform measurements if one of the discrete measurement scenarios are configured. figure 3 . 3 structure of th e sleep timer prescaler 1 : 12500 16-bit counter 12-bit counter lpclk (125 khz) cntclk (10 hz) == ? == ? sleeptcmp (register file) sleeptadccmp (register file) sleeptcurcnt (register file) stirq (irq ctrl) stadctrigger (pmu) when the system goes from the full - power (fp) state to any power - down state on request by the user, the prescaler and both counters are cleared and the 16 - bi t counter is enabled. every 100 ms, triggered by the pre - scaler, the 16 - bit counter is incremented until it reaches the programmed compare value sleeptcmp . when the compare value is reached, the timer stops and the interrupt controller is triggered to set the corresponding status flag (see section 3.6.1.1 ) . the sleep timer is also stopped when the system returns to the fp state . the user can determine the sleep duration by reading the registe r sleeptcurcnt, which returns the value of the 16 - bit counter (see table 3 . 15) . note: although the timer stops and the interrupt status bit is set when the compare value is reached, the system remains in the power - down state if the corresponding interrupt is not enabled to drive the interrupt line irqn ( bit 1 in the irqena register; see table 3 . 17 ) .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 44 april 20, 2016 equation (2 ) can be used to determine the correct sleep time to be programmed . t h e sleep timer expires after 100ms for a compare value of 0, aft er 200 ms for a compare value of 1 , and so on. ( ) 1 100ms time sleep + ? = sl eeptcmp ( 2 ) the 12 - bit counter that triggers the pmu is only enabled during any power - down state when any discrete measurement scenario is configured. in this case, the counter is incremented each 100ms triggered by the prescaler. when the counter reaches the programmed compare value sleept adccmp, a strobe for the pmu is generated and the 12 - bit counter is reset to 0. then it continues its operation. this counter is only stopped when the system returns to the fp s tate, but it continues to operate when the sleep timer has expired if it was not enabled to wake up the system. equation (3 ) can be used to determine the correct adc trigger time to be programmed . t he adc trigger timer expires after 100 ms for a compare value of 0, after 200 ms for a compare value of 1, and so on. in general ( ) 1 100ms time trigger adc + ? = mp sl eeptadcc ( 3 ) important : when both the sleep timer for wake - up and the adc trigger timer for discrete measurements are used, special care must be taken when programming the compare values because when the sleep timer expires , the wake - up condition has higher priority over an active adc measu rement or an adc trigger strobe. 3.5.1 sleep timer registers 3.5.1.1 register ?sleeptadccmp? ? compare value for adc trigger timer table 3 . 13 register sleeptadccmp name addr bits default access description sleeptadccmp[7:0] 60 hex [7:0] 0 0 hex rw lower byte of compare value for the adc trigger timer; the adc trigger timer is only active if the system is in lp or ulp s tate and any discrete measurement scenario is configured generating periodic strobes for the pmu. adc trigger time = 100 ms ? ( sleeptadccmp + 1) sleeptadccmp[15:8] 61 hex [7:0] 0 0 hex rw upper byte of compare value for adc trigger timer; adc trigger timer is only active when the system is in lp or ulp s tate and any discrete measurement scenario is configured generating periodic strobes for the pmu. adc trigger time = 100 ms ? ( sleeptadccmp + 1)
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 45 april 20, 2016 3.5.1.2 register ?sleeptcmp? ? compare value for sleep timer table 3 . 14 register sleeptcmp name addr bits default access description sleeptcmp[7:0] 62 hex [7:0] 00 hex rw lower byte of compare value for sleep timer; sleep timer is only active if the system is in lp or ulp s tate. sleep time = 100 ms ? ( sleeptcmp + 1) sleeptcmp[15:8] 63 hex [7:0] 00 hex rw upper byte of compare value for sleep timer; sleep timer is only active when the system is in lp or ulp s tate. sleep time = 100 ms ? ( sleeptcmp + 1) 3.5.1.3 register ?sleeptcurcnt? ? current value of sleep timer table 3 . 15 register sleeptcurcnt name addr bits default access description sleeptcurcnt[7:0] 20 hex [7:0] 00 hex ro lower b yte of the current sleep timer value. since the timer is stopped in fp state , the duration of the last power - down state can be determined: sleep time = 100 ms ? ( sleeptcurcnt + 1) note: v alue is only valid when ssw[1] ( sleep timer valid stvalid) is set . sleeptcurcnt[15:8] 21 hex [7:0] 00 hex ro upper b yte of the current sleep timer value. since the timer is stopped in fp state , the duration of the last power - down state can be determined: sleep time = 100 ms ? ( sleeptcurcnt + 1) note: v alue is only valid when ssw[1] (stvalid) is set . 3.6 sbc interrupt controller (irq_ctrl block) there are 16 different interrupt sources in the sbc system, each having a dedicated interrupt status bit in the irqstat register (see table 3 . 16) and a dedicated interrupt enable bit in the irqena register (see table 3 . 17) . the interrupt controller captures each interrupt source in the interrupt status register independently of the interrupt enable settings. the interrupt controller combines all enabled interr upt status bits into the low - active interrupt signal that is used to drive the interrupt pin irqn of the sbc and to wake up the system by the pmu . this means that interrupt status bits, which can always be set even when disabled, can only generate a wake - u p event and drive the interrupt pin irqn when they are enabled.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 46 april 20, 2016 figure 3 . 4 generation of interrupt and wake - up irqstat [ 0 ] irqena [ 0 ] & irqstat [ 15 ] irqena [ 15 ] & . . . o r irqn wake - up ( to pmu ) the user can determine the interrupt reason by reading the interrupt status register irqstat. the interrupt status register is cleared on each read access. therefore the user?s software must ensure that it stores the read interrupt status value if needed to avoid loss of information. 3.6.1.1 interrupt sources the bit mapp ing is the same for the interrupt enable register irqena (see table 3 . 17 ) a nd the interrupt status register irqstat (see table 3 . 16 ) : bit 0: watchdog timer interrupt ; status is set by the watchdog timer when the interrupt functionality of the watchdog timer is enabled an d the watchdog timer expires for the first time. bit 1: sleep timer interrupt ; status is set by the sleep timer when the sleep timer reaches the programmed compare value. bit 2: lin txd timeout interrupt (for zssc1750 only ) ; status is set by the lin support logic when the txd input from the external microcontroller is low for more than 10 .24 ms. bit 3: lin short interrupt (for zssc1750 only ) ; status is set by the lin support logic when a short is detected in the lin phy. bit 4: lin wakeu p interrupt (for zssc1750 only ) ; status is set by the lin support logic when a wake - up frame is detected on the lin bus. bit 5: current conversion result ready interrupt ; status is set by the adc unit when a single current measurement (register adccrcl == 0) or multiple current measurements defined by adccrcl (register adccrcl 0) have been completed and the result is available.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 47 april 20, 2016 bit 6: voltage conversion result ready interrupt ; status is set by the adc unit when a single voltage measurement (register adcvr cl == 0) or multiple voltage measurements defined by the adcvrcl (register adcvrcl 0) have been completed and the result is available. bit 7: temperature conversion result ready interrupt ; status is set by the adc unit when a single temperature measurement has been completed and the result is available. bit 8: current comparator interrupt ; status is set by the adc unit when the c urrent t hreshold c ounter m ode is enabled (register adcacmp[2:1] 0 0) and the absolute value of multiple current measurements (defined by register adcctcl) exceeds the programmed current threshold (register adccrth) . note: if the threshold counter mode is enabled but adcctcl is 0, this bit is always set indepen - dently of the th reshold. bit 9: voltage comparator interrupt ; status is set by the adc unit if the vthwuena bit ( adcacmp[8] ) is set to 1 and a single measured voltage or the accumulated voltage measurements (depends on configured mode) drop below the programmed (register adcvth ) voltage threshold. bit 10: temperature threshold interrupt ; status is set by the adc unit when the twuena bit ( adcacmp[10] ) is set to 1 and a temperature measurement is outside the specified temperature interval defined by registers adctmin and adctmax. bit 11: current accumulator threshold interrupt ; status is set by the adc unit when the caccuthena bit ( adcacmp[3] ) is set to 1 and the accumulated current values rise above t he programmed threshold value (register adccaccth ) for a positive threshold value or fall below the programmed threshold value for the negative threshold value. bit 12: current overflow interrupt ; status is set by the adc unit when the covrena bit ( adcacmp[4] ) is set to 1 and the compensated value of a current measurement is outs ide of the representable range. bit 13: voltage/ temperature overflow interrupt ; status is set by the adc unit when the vtovrena bit ( adcacmp[5] ) is set to 1 and the compensated value of a voltage or temperature measurement is outside of the representable r ange. bit 14: current over - range interrupt ; status is set by the adc unit when the covrena bit ( adcacmp[4] ) is set to 1 and the input from the current adc is overdriven. bit 15: voltage/ temperature over - range interrupt ; status is set by the adc unit when the vtovrena bit ( adcacmp[5] ) is set to 1 and the input from the voltage/ temperature adc is overdriven.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 48 april 20, 2016 3.6.1.2 register ?irqstat? ? interrupt status register table 3 . 16 register irqstat name address bits default access description irqstat[7:0] 00 hex [7:0] 00 hex rc lower byte of the interrupt status register as defined in section 3.6.1.1 ; each bit is set by hardware and cleared on read access . irqstat[15:8] 01 hex [7:0] 00 hex rc upper byte of interrupt status register as defined in section 3.6.1.1 ; each bit is set by hardware and cleared on read access . note: t o avoid loss of information, t he hardware set condition has a higher priorit y than the read clear condition . 3.6.1.3 register ?irqena? ? interrupt enable register table 3 . 17 register irqena name address bits default access description irqena[7:0] 54 hex [7:0] 00 hex rw lower byte of the interrupt enable register as defined in section 3.6.1.1 ; only enabled interrupts can drive the interrupt line and wake up the system; the bit mapping is the same as for the interrupt status register . irqena[15:8] 55 hex [7:0] 00 hex rw upper byte of the interrupt enable register as defined in section 3.6.1.1 ; only enabled interrupts can drive the interrupt line and wake up the sys tem; the bit mapping is the same as for the interrupt status register . note: the interrupt enable bit for the lin wake - up interrupt ( irqena[4] ) is also used as the enable for the lin wake - up (for zssc1750 only ) frame detector within the pmu.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 49 april 20, 2016 3.7 sbc power management unit ( sb c_pmu block ) the power management unit (pmu) controls placing the sbc into the selected power down state, controlling the power down signals for the different analog blocks , and controlling the clocks for the digital logic. i t also cont rols the other digital modules during the power - down state. the system provides four different power states : fp (f ull - p ower s tate) in this state, all blocks are powered except the adcs if the user?s software has not enabled them. a ll internal clocks are active (divclk and muxclk are 4mhz) and the external microcontroller is also powered and clocked through pins vddp, vddc, and mcu_clk . when powered and enabled by software, the adc clocks are generated from the clock from the high - pr ecision oscillator. lp ( l ow - p ower s tate) in this state, the high - precision oscillator and the lin transmitter (zssc1750 only) are powered down. the clock for the external microcontroller (mcu_clk) is stopped , but the microcontroller remains powered through vddp and/or vddc . d epending on the selected measurement scenario, the adcs are also powered down during times of inactivity. otherwise the adc clocks are generated from the low - power oscillator. ulp ( u ltra - l ow - p ower s tate) in this state, the high - precision oscillator and the lin transmitter (zssc1750 only) are powered down. the optional external microcontroller clock mcu_clk is stopped and the supply voltages for the external microcontroller ( vddp, vddc ) are powered down. d e pending on the selected measurement scenario, the adcs are also powered down during times of inactivity. otherwise , the adc clocks are generated from the clock from the low - power oscillator. off ( o ff s tate) in this state, all analog blocks except the digit al power supply for the sbc and the rx part of the lin phy (zssc1750 only) are powered down. the external microcontroller clock mcu_clk is stopped , and the supply voltages for the external microcontroller ( vddp, vddc ) are powered down. for the zssc1750/51 to enter any of the power - down states (lp, ulp , or off), the user?s software must first set the pdstate field of register pwrcfglp to select the state (see table 3 . 19) and enable th e interrupts needed as the wakeup source before writing a9 hex to register gotopd (see table 3 . 20). immediately after a9 hex is written to the gotopd register, the csn line must be driven high. although for all other register accesses , the csn line can be kept low and the next spi transfer can follow immediately, it is mandatory to drive csn high for the power - down command. otherwise, the pmu remains in the fp s tate. important : if no interrupt is enabled, the system can only be awakened by power - on- reset! note: t he csn line mus t be driven high to go to power - down after writing the value a9 hex to register gotopd .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 50 april 20, 2016 the following tasks are always performed on transition to any power - down state by the pmu: ? both adcs are stopped. an y active measurement is interrupted. adc control is transferred to the pmu. ? those configuration values that can be configured independently for the full - power state and power - down state s are switched to the power - down settings. ? the sleep timer is cleared and enabled. ? the clock on the mcu_clk pin is stopped. ? the h igh - precision oscillator is powered down. ? the tx part of the lin phy is powered down (zssc1750 only) . ? the source for the muxclk changes from divclk to lpclk. if any of the enabled interrupts occurs and the interrupt pin irqn is driven low, the system wakes up immediately ; any adc measurement that is active during the power - down state is stopped. all mandatory blocks are powered up , and the system waits for stabilization before re - enabling the clock output mcu_clk for the external microcontroller . if any of the enabled interrupts is already active on reception of the power - down command or becomes acti ve on transition to the requested power - down state, the system rejects the power - down command or re - enables those blocks that are already powered down. depending on the time whe n the power - down procedure was interrupted, it is possible that the sleep timer was not cleared. in this case, the sleep timer valid flag is cleared , signal ing that the sleep timer value in register sleeptcurcnt is not valid. this flag is mapped to ssw[1]. 3.7.1 fp state after the initial power - on reset when the otp content s are downloaded into the registers and all blocks have stabilized, the system enters the fp s tate. in this state, all voltage regulators, both oscillators and the lin phy (zssc1750 only) are powered but the adcs are still powered down. important : both adcs are po wered down after power - on reset. to be able to use the adcs, the user must first power up the required adcs by programming register pwrcfgfp , bits pwradci and/or pwradcv (see table 3 . 18 ). the first bit enables the current adc and the second bit enables the voltage/temperature adc. in this register are three other bits that can be set by the user , but they should be handled with care as the system con sumes less power when any of these bits is set but the accuracy of the measurement results is reduced: ? lpenafp if set to 1, the bias current for analog blocks is reduced to 10% ? ulpenafp if set to 1, the bias current for analog blocks is reduced to 5% ? pdrefbufocfp if set to 1, the offset cancellation circuit inside the reference buffer is powered down note: if both lpenafp and ulpenafp are set to 1, the bias current for analog blocks is reduced to 15%. important : these settings are only used in fp s tate . for configuration for the power - down states, the pwrcfglp register must be used. the settings in register pwrcfgfp are preserved when entering any power - down state by executing the power - down command. the pmu overrides these settings or switches to the s ettings made in register pwrcfglp on transition to the power - down state. when the system wakes up and returns to the fp s tate, the pmu restores the settings as configured in pwrcfgfp regardless of whether any adc was powered in power - down state or not.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 51 april 20, 2016 3.7.2 lp and ulp state s the lp and ulp power - down states are used to save power while doing measurements with lower accuracy. in both states, the tx part of the lin phy and the high - precision oscillator are powered down and the external microcontroller clock is sto pped. the internal clock muxclk is driven by the low - power osc illator with a frequency of 125 khz while the internal clock divclk is stopped. in ulp s tate, the two voltage regulators vddp (io voltage for sbc and external microcontroller ) and vddc ( optional core voltage for external microcontroller ) are powered down. in this case, the sleepn pin is driven low to indicate this state . the state of the adcs and the other analog blocks needed for measurements depend s on the configured measurement setup for the po wer - down state (see following sub sections ). the blocks are powered when they are needed for measurement and powered down when they are not needed for measurement. this is controlled by the pmu as well as the control signals ( start, stop, mode ) for the digi tal adc unit. the main configuration register for the power - down behavio r is register pwrcfglp (see table 3 . 19 ). the field pdstate is used to select the power - down state to be entered on reception of the power - down command , and the field pdmeas is used to define the measurement setup to be used during the power - down state. there are three other bits to configure the power - down behav io r : ? lpenalp if set to 1, the bias current for analog blocks is reduced to 10% ? ulpenalp if set to 1, the bias current for analog blocks is reduced to 5% ? pwrrefbufoclp if set to 1, the offset cancellation circuit in the reference buffer is powered up note: if both lpenalp and ulpenalp are set to 1, the bias current for analog blocks is reduced to 15%. for the corresponding bits for the fp s tate , lpenaf p and ulpenaf p in register pwrcfgfp (see table 3 . 18), the meaning is the same, but the default setting s are different. while there is no bias current reduction during fp s tate ( default setting for both bits is 0), the default bias current for the lp and ulp s tate s is reduced to 10%. the meaning of the control bit for the offset cancellation differs : t he fp s tate control bit is a power - down signal ; the lp/u lp s tate control bit is a power - up bit. while the offset cancellation is enabled by defaul t during the fp s tate ( pdrefbufocfp == 0), the offset cancellation is disabled by default during the lp or ulp s tate ( pdrefbufoclp == 0) . both bits are configurable by the user. on transition to the lp or ulp s tate, the sleep timer and the adc trigger timer are cleared. while the sleep timer is always enabled during power - down state s , the adc trigger timer is only enabled when performing discrete measurements. if the sleep timer interrupt is enabled, the system wakes up when the sleep timer expires. if the sleep timer interrupt is not enabled, the sleep timer stops when it expires , but the adc trigger timer, if enabled due to the measurement configuration , continues its operation . f or wake - up, other interrupts must be enabled ; e.g. , lin wakeup (for zssc1 750 only ) . note: t he sleep timer is always active during the lp and ulp s tate s . note: when reading t he sleep timer value after wake - up by another enabled interrupt, the sleep timer is only valid when it has not reached its compare value although the valid flag says valid. whether the sleep timer is valid can be determined by the sleep timer status bit. when the system wakes up and returns to fp s tate, the sleep timer is stopped. the user?s s oftware can read the sleep timer value to determine the duration of the power - down state.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 52 april 20, 2016 3.7.2.1 performing n o measurement s during lp/ulp state when the lp or ulp s tate has been entered, all analog blocks related to adcs are powered down. i f the system goes to power down without performing any measurements, only three different wake - up sources are possible : the watchdog timer interrupt, the sleep timer interrupt , and the lin wakeup interrupt (for zssc1750 only ) . important: at least one of these interrupts must be enabled , as otherwise the system can only wake up via power - on re set. if no inter rupt is enabled, the system can not wake up . to go to lp or ulp s tate without performing measurements, the following tasks must be done: ? enable at least one of the following interrupts: ? set irqena[0] to 1 to enable the watchdog interrupt to wake up the system. ? set irqena[1] to 1 to enable the sleep timer to wake up the system. ? set irqena[4] to 1 to enable the lin wake - up detector and to enable the system to wake up due to a lin wakeup frame (for zssc1 750 only ) . ? set up the sleep timer compare value (register sleeptcmp ) if needed. ? configure the pwrcfglp register as follows: ? set pdstate to 0 or 1 to configure the lp s tate or to 2 to configure the ulp s tate. ? set pdmeas to 0 to configure the system to perform no measurements. ? set lpenalp, ulpenalp and pwrrefbufoclp as needed. ? write a9 hex to register gotopd and then drive the csn line high. when an enabled interrupt occurs, the system wakes up and the settings from regist er pwrcfgfp are restored. when all blocks have stabilized, the external microcontroller clock mcu_clk is re - enabled , and if coming out of the ulp s tate, the microcontroller reset mcu_rst is released. figure 3 . 5 lp/ ulp s tate without any m easurements note: the sleep timer is used as the wake - up source in this example , but it could also be the watchdog timer interrupt or the lin wakeup interrupt. fp fp lp / ulp wa keup due to sleep timer interrupt i t gotopd c ommand
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 53 april 20, 2016 3.7.2.2 performing discrete measurements of current during lp/ulp state the system can be configured to periodically enable the current adc and to measure the c urrent during the lp or ulp s tate. the current adc can be configured to perform several current measurements during each measurement phase (green box es in figure 3 . 6 ). upon entering the lp / ulp s tate and between the measurements, the current adc is powered dow n. the voltage/ temperature adc is powered down for the entire power - down period. the pmu powers up the current adc when triggered by the adc trigger timer. possible wake - up sources during this scenario are the watchdog timer interrupt, the sleep timer interrupt, the lin wakeup interrupt (for zssc1750 only ) , or any of the adc interrupts related to curre nt. important : when no inter rupt is enabled, the system can not wake up. to go to lp or ulp s tate and perform discrete current measurements, the following tasks must be done: ? enable at least one of the following interrupts: ? set irqena[0] to 1 to enable the watchdog interrupt to wake up the system. ? set irqena[1] to 1 to enable the sleep timer to wake up the system. ? set irqena[4] to 1 to enable the lin wake - up detector and to enable the system to wake up due to a lin wakeup frame (for zssc1750 only ) . ? enable any adc interrupt related to current (see section 3.6.1.1 ) . ? set up the sleep timer compare value (register sleeptcmp ) if needed. ? set up the a dc trigger timer compare value (register sleeptadccmp ) as needed. ? configure the pwrcfglp register as follows: ? set pdstate to 0 or 1 to configure lp s tate or to 2 to configure ulp s tate. ? set pdmeas to 1 to configure the system to perform discrete current me asurements. ? set lpenalp, ulpenalp and pwrrefbufoclp as needed. ? write a9 hex to register gotopd and then drive the csn line high . when an enabled interrupt occurs, the system wakes up and the settings from register pwrcfgfp are restored. when all blocks have stabilized, the external microcontroller clock is re - enabled and, if coming out of ulp s tate, the microcontroller reset is released. important : if any measurement is active while an enabled interrupt occurs ( e.g. , the sl eep timer expires ), the measurement is interrupted and the system returns to fp s tate. in the example shown in figure 3 . 6 , the first wakeup is by the a dc and the second wake - up is by the sleep timer ; however, the wakeups could be other combinations of the watchdog timer interrupt, sleep timer interrupt, and/or lin wakeup interrupt (zssc1750 only).
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 54 april 20, 2016 figure 3 . 6 lp/ ulp s tate p erforming only c urrent m easurements fp fp lp / ulp wakeup due to sleep timer interrupt current wakeup fp lp / ulp i t adc trigger time gotopd command gotopd command current only measurements 3.7.2.3 performing discrete measurements of current, voltage , and internal temperature during lp/ulp state during the lp or ulp state, t he system can be configured to periodically enable both adcs and measure current, voltage , and inter nal or external temperature (see section 3.7.2.4 for external temperature) . th e sequence c an be selected in the pdmeas bit field [4:2] in register pwrcfglp , which also selects whether internal or external temperature is measured. the period between each measurement is determined by the adc trigger timer ( sleeptadccmp) . the current adc can be c onfigured to perform multiple current measurements during each measurement window (green and orange box es in figure 3 . 7 to figure 3 . 9 ) while the voltage/ temperature adc can be configured to perform multipl e voltage or internal temperature measurements (orange box es in figure 3 . 7 to figure 3 . 9 ). after performing the configured number of voltage measurements, the pmu changes th e configuration for the voltage/ temperature adc and performs a single measurement of the internal temperature. voltage and temp erature are not measured in each sample period if the adcs are configured for measuring only current in a specified number of initial loops . the user can configure register disccvtcnt (see table 3 . 21) so that in the first disccvtcnt samples , only current is measured before voltage and temperature are measured in the next sample . upon entering the lp/ ulp s tate and between the measurements, both adcs are powered down. the pmu powers up the current adc when triggered by the a dc trigger timer. the voltage/ temperature adc is only powered up after disccvtcnt current - only measurements have been performed. possible wake - up sources in this setup ar e all interrupts except lin short and lin txd timeout interrupts (zssc1750 only) . important : when no inter rupt is enabled, the system can not wake up .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 55 april 20, 2016 to go to the lp or ulp s tate and perform measurements of discrete current, voltage , and internal temperature, the following tasks must be done: ? enable at least one of the following interrupts: ? set irqena[0] to 1 to enable the watchdog interrupt to wake up the system. ? set irqena[1] to 1 to enable the sleep timer to wake up the system. ? set irqena[4] to 1 to enable lin wake - up detector and to enable the system to wake up due to a lin wakeup frame (for zssc1750) . ? enable any adc interrupt (see section 3.6.1.1 ) . ? configure the sleep timer compare value (register sleeptcmp ) if needed. ? set up the adc trigger timer compare value (register sleeptadccmp ) as needed. ? configure the pwrcfglp register as follows: ? set pdstate to 0 or 1 to configure the lp s tate or to 2 to configure the ulp s tate. ? set pdmeas to 2 to configure the system to perform discrete current, voltage , and internal temperature measurements. ? set lpenalp, ulpenalp and pwrrefbufoclp as needed. ? set disccvtcnt as needed. this register defines the number of current - only measurement loops before performing measurement s of all three parameters. ? write a9 hex to register gotopd and then drive the csn line high. when an enabled interrupt occurs, the system wakes up and the settings from regis ter pwrcfgfp are restored. when all blocks have stabilized, the external microcontroller clock is re - enabled and if coming out of the ulp s tate, the microcontroller reset is released. important : if any measurement is active while an enabled interrupt occurs ( e.g. , the sleep timer expires) the measurement is interrupted and the system returns to the fp s tate. note: if register disccvtcnt is set to 0, voltage and temperature are measured in each loop (default setting) .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 56 april 20, 2016 figure 3 . 7 lp /ulp s tate p erforming c urrent, v oltage , and t emperature m easurements with disccvtcnt == 2 fp fp lp / ulp wakeup due to sleep timer interrupt current measurement only measurement of current, voltage and temperature i t adc trigger time gotopd command figure 3 . 8 lp /ulp state performing current, volta ge , and temperature measurements with disccvtcnt == 5 fp fp lp / ulp wakeup due to v oltage , t emperature or c urrent adc interrupt c urrent measurement only m easurement of current , voltage , and temperature i t adc t rigger t ime gotopd c ommand
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 57 april 20, 2016 figure 3 . 9 lp/ulp s tate p erforming c urrent, v oltage , and t emperature m easu rements with disccvtcnt == 1 fp fp lp / ulp w akeup due to current adc interrupt c urrent measurement only m easurement of current , voltage and temperature i t adc t rigger t ime gotopd c ommand 3.7.2.4 performing discrete measurements of current, voltage , and external temperature during lp/ulp state during the lp or ulp state, t he system can be configured to periodically enable both adcs and measure current, voltage, and external temperature . this setup is the same as the configuration described in the previous section , except that the external instead of the internal temperature is measured. to use this option, pdmeas must be set to 3. 3.7.2.5 perfor ming continuous measurements of current during lp/ulp state the system can be configured to perform continuous current measurements during the lp or ulp s tate. while the current adc is powered up during the entire power - down state, the voltage/ temperature adc is powered down. the current adc is powered up on entering the lp/ ulp s tate if it was not already powered up during the fp s tate. the adc trigger timer is not enabled as the measurement is continuous. possible wake - up sources during this scenario are the watchdog timer interrupt, the sleep timer interrupt, the lin wakeup interrupt (for zssc1750 only ) , or any of the adc interrupts related to current. important: if no inter rupt is enabled, the system can not wake up.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 58 april 20, 2016 to go to the lp or ulp s tate with cont inuous current measurements, the following tasks must be done: ? enable at least one of the following interrupts: ? set irqena[0] to 1 to enable the watchdog interrupt to wake up the system. ? set irqena[1] to 1 to enable the sleep timer to wake up the system. ? s et irqena[4] to 1 to enable the lin wake - up detector and to enable the system to wake up due to a lin wakeup frame (for zssc1750 only ) . ? enable a ny adc interrupt related to current (see section 3.6.1.1 ) . ? setup the sleep timer compare value (register sleeptcmp ) if needed. ? configure the pwrcfglp register as follows: ? set pdstate to 0 or 1 to configure lp s tate or to 2 to configure ulp s tate. ? set pdmeas to 4 to configure the system to perform continuous current measurements. ? set lpenalp, ulpenalp, and pwrrefbufoclp as needed. ? write a9 hex to register gotopd and then drive the csn line high. when an enabled interrupt occurs, the system wakes up and the set tings from register pwrcfgfp are restored. when all blocks have stabilized, the external microcontroller clock is re - enabled and if coming out of ulp s tate, the microcontroller reset is released. important: if any measurement is active while an enabled int errupt occurs (e.g., the sleep timer expires) , the measurement is interrupted and the system returns to fp s tate. figure 3 . 10 lp/ ulp s tate p erforming c ontinuous c urrent - only m easurements note: the sleep timer interrupt or an adc interrupt related to current is used as the wake - up source in this example, but it could also be the watchdog timer interrupt or the lin wakeup interrupt (zssc1750 only). fp fp lp / ulp wakeup due to sleep timer or current adc interrupt c urrent measurement only i t gotopd c ommand
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 59 april 20, 2016 3.7.2.6 performing continuous current and voltage measurements during lp/ulp state the system can be configured to perform continuous current and voltage measurements during the lp or ulp s tate. both adcs are powered up during the entire power - down state. the adcs are powered up on entering the lp/ ulp s tate if they were not already powered up during the fp s tate. the adc trigger timer is not enabled as the measurement is continuous. possible wake - up sources during this scenario are the watchdog timer interrupt, the slee p timer interrupt, the lin wakeup interrupt (for zssc1750 only ) , or any of the adc interrupts related to current or voltage. important : if no interr upt is enabled, the system can not wake up. to go to lp or ulp s tate and perform continuous current and volta ge measurements, follow these steps : ? enable at least one of the following interrupts: ? set irqena[0] to 1 to enable the watchdog interrupt to wake up the system. ? set irqena[1] to 1 to enable the sleep timer to wake up the system. ? set irqena[4] to 1 to enabl e the lin wake - up detector and to enable the system to wake up due to a lin wakeup frame (for zssc1750 only ) . ? enable a ny adc interrupt related to current. ? set up the sleep timer compare value (register sleeptcmp ) if needed. ? configure the pwrcfglp register as follows: ? set pdstate to 0 or 1 to configur e the lp s tate or to 2 to configure the ulp s tate. ? set pdmeas to 5 to configure the system to perform continuous current and voltage measurements. ? set lpenalp, ulpenalp, and pwrrefbufoclp as needed. ? write a9 hex to register gotopd and then drive the csn line high . when an enabled interrupt occurs, the system wakes up and the settings from register pwrcfgfp are restored. when all blocks have stabilized, the external microcontroller clock mcu_clk is re - e nabled and if coming out of ulp s tate, the microcontroller reset mcu_rst is released. important: if any measurement is active while an enabled interrupt occurs ( e.g. , the sleep timer expires ) , the measurement is interrupted and the system returns to the fp s tate.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 60 april 20, 2016 figure 3 . 11 p erforming c ontinuous c urrent and v oltage m easurements during lp/ulp state note: the sleep timer interrupt or an adc interrupt related to voltage or current is used as the wake - up sourc e in this example, but it could also be the watchdog timer interrupt or the lin wakeup interrupt (for zssc1750 only). fp fp lp / ulp w akeup due to s leep t imer , v oltage adc , or current adc interrupt m easurement of current and voltage i t gotopd c ommand 3.7.2.7 performing continuous measurements of current and internal temperature during lp/ulp state this setup is the same as the configuration described in the previous section , except that the internal tem - perature instead of the voltage is measured. to use this option, pdmeas must be set to 6. possible wake - up sources during this scenario are the watchdog timer interrupt, the sleep timer interrupt, the lin wakeup interrupt (for zssc1750 only ) , or any of the adc interrupts related to current or temperature. 3.7.2.8 performing continuous measurements of current and external temperature during lp/ulp state this setup is the same as the configuration described in the previous section , except that the external temperature instead of the internal temperature is measured. to use this option, pdmeas must be set to 7. possible wake - up sources during this scenario are the watchd og timer interrupt, the sleep timer interrupt, the lin wakeup interrupt (for zssc1750 only ) , or any of the adc interrupts related to current or temperature. 3.7.3 off state the off s tate is the power - down state with the lowest current consumption , and no adc mea surements are possible. it is intended for long periods of inactivity ; e.g. , when a car is shipped around the world. during this state , all oscillators and clocks are turned off, the external microcontroller is not powered , and most of the analog blocks ar e powered down. only the sbc?s digital core and the rx part of the lin phy remain powered. the system can only wake up at the detection of a lin wakeup frame (for zssc1750 only ) or after power - on reset (for zssc1750/51) . to go to the off s tate, the followi ng tasks must be done: ? set irqena[4] to 1 to enable the lin wake - up detector and to enable the system to wake up due to a lin wakeup frame (for zssc1750 only ) . ? set pdstate to 3 to configure the off s tate as the power - down state to be entered. ? write a9 hex to register gotopd and drive the csn line high.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 61 april 20, 2016 for the zssc1750 only, w hen the lin rxd line goes low during the off s tate, the low - power oscillator is re - enabled and the digital logic checks if the lin rxd line is low for a time equal or more than 150s. if this is true, the complete system returns to the fp s tate and the external microcontroller is powered up , reset , and c locked again. i f the lin rxd line was low for less than 150s, the low - power oscillator is powered down again and the system remains i n off s tate. important: if the lin wakeup int e rrupt is not enabled, the system only can only wake up by a power - on reset. 3.7.4 registers for power configuration and the discreet current measurement count 3.7.4.1 register ?pwrcfgfp? ? power configuration register for the fp state table 3 . 18 register pwrcfgfp name address bits default access description pwradci 53 hex [0] 0 bin rw when set to 1, the current adc is powered. pwradcv [1] 0 bin rw when set to 1, the voltage/ temp erature adc is powered. r eserved [2] 0 bin rw r eserved; always write as 0 . lpenafp [3] 0 bin rw when set to 1, the bias current of the analog blocks is reduced to 10% in the fp s tate. note: if ulpenafp is also set to 1, the bias current of the analog blocks is reduced to 15%. ulpenafp [4] 0 bin rw when set to 1, the bias current of the analog blocks is reduced to 5% in the fp s tate. note: if lpenafp is also set to 1, the bias current of the analog blocks is re duced to 15%. pdrefbufocfp [5] 0 bin rw when set to 1, the offset cancellation of the reference buffer is powered down. u nused [7:6] 0 0 bin ro u nused; always write as 0 .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 62 april 20, 2016 3.7.4.2 register ?pwrcfglp? ? power configuration register for power - down states table 3 . 19 register pwrcfglp name address bits default access description pdstate 64 hex [1:0] 0 0 bin rw s elect the power - down state to be entered : 0 or 1 lp s tate 2 ulp s tate 3 off s tate pdmeas [4:2] 0 0 0 bin rw t ype of measurements to be performed during the lp or ulp s tate : 0 n o measurements 1 d iscrete measurements of current 2 d iscrete measurements of current, voltage , and internal temperature 3 d iscrete measurements of current, voltage , and external temperature 4 c ontinuous measurements of current 5 c ontinuous measurements of current and voltage 6 c ontinuous measurements of current and internal temperature 7 c ontinuous measurements of current and external temperature lpenalp [5] 1 bin rw when set to 1, the bias current of the analog blocks is reduced to 10% in the lp/ulp s tate. note: if ulpenalp is also set to 1, the bias current of the analog blocks is reduced to 15%. ulpenalp [6] 0 bin rw when set to 1, the bias current of the analog blocks is reduced to 5% in the lp/ulp s tate. note: i f lpenalp is also set to 1, the bias current of the analog blocks is just reduced to 15%. pwrrefbufoclp [7] 0 bin rw when set to 1, the offset cancellation of the reference buffer is powered in lp/ulp s tate while performing measurements.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 63 april 20, 2016 3.7.4.3 register ?gotopd? ? enter power - d own state table 3 . 20 register gotopd name address bits default access description gotopd 65 hex [7:0] 0 0 hex wo writing a9 hex to this register triggers the pmu to enter the configured power - down state when the csn line is driven high. 3.7.4.4 register ?disccvtcnt? ? configuration register for discrete measurements table 3 . 21 register disccvtcnt name add ress bits default access description disccvtcnt 5 f hex [7:0] 00 hex rw d efines the number of "current only" measurements before performing one measurement of current, voltage , and temperature when pdmeas is 2 or 3 . 3.8 zssc1750/51 adc unit the measurement subsystem incorporates two independent and synchronized high - resolution adcs for monitoring two channels (sd_adc blocks) . the conversion scheme is based on the s igma - d elta m odulation (sdm) principle. one channel (adc - i) is exclusively used for current measurement and includes a pre - amplifier with offset cancellation circuitry. the second channel (adc - v/t) can be programmed for measuring either voltage or temperature (internal or external). the raw conversion data can be post - processed by calibration dat a to achieve a minimum offset and gain error (gain and offset correction). the conversion results are stored in the register file from w hich they can be read via the spi digital communication interface. a completed conversion is flagged by a ? data ready ? s ignal that can be used as an interrupt source for the external microcontroller . a functional block diagram of the analog circuitry is shown in figure 3 . 12 . the purpose of this analog architecture is to achieve a maximum level of diagnostic capability and flexibility as well as best accuracy. the digital adc unit consists of the data processing unit and control logic. the control logic generates the clo cks and control signals for the analog sd - adcs as well as control signals for the data processing part of the adc unit.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 64 april 20, 2016 figure 3 . 12 functional block diagram of the analog measurement subsystem pga-1 pa-c on- chip temperature sensor pa-t sinc 4 digital filter mpx3 inp inn vssa vssa vbat nth vdda ntl vssa vcm vcm f isc f isc v ref 1.2v vssa i m vssa f int / f dec vdda r ntc c vda vcm=v dda /2 analog-2-digital conversion pdexttemp pd_vbat csel pd_inamp vtsel csel mpx2 mpx1 sc-clock generator f sdm sinc 4 digital filter f int / f dec f isc pga-2 sg - modulator-1 sg - modulator-2 i pz1 i pz2 i pz3 i pz4 r ref v reflp 1.2v v ref 1.2v vptat vbatp vbatn pa- c = preamplifier current; pa - t = preamplifier temperature; mpx = multiplexer; pga = programmable gain amplifier 3.8.1 adc clocks two clocks are generated in the digital part of the adc unit and are driven to the analog part. the sdm clock is used for both sd - adcs. the chop clock is used for the chopping operation within the sd - adcs. the base for both clocks is the multiplexed clock muxclk , which is a 4 mhz clock in fp s tate and a 125 khz clock in lp/ ulp s tate. 3.8.1.1 adc clocks in fp stat e in the fp s tate, the sdm clock is generated from the 4 mhz clock by dividing it by two times the value prog - rammed into bit field sdmclkdivfp in register sdmclkcfgfp (see table 3 . 24) : mhz 4 f 2 f f hp hp sdm = ? = ( 4 ) important : when sdmclkdivfp is set to 0, the frequency of sdm clock is 2 mhz.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 65 april 20, 2016 the chop clock is generated from the sdm clock by further dividing it by 2, 4, 8 , or 16 depending on the setting of the sdmchopclkdiv field in register adcgomd (see table 3 . 55) : ) 1 div sdmclkchop ( sdm chop 2 f f + - ? = ( 5 ) although the clock bases used to generate the sdm and the c hop clock have a frequency of 4 mhz, the position of the clock edges used for the clock generation c an be shifted relative to the 4 mhz clock used for the digital logic to obtain optimal noise behavior for the analog section . the 4 mhz clock used to generate the sdm clock (clk sdmbase ) is delayed relative to the 4 mhz clock used for the digital logic (clk muxclk ) by one to four 20 mhz clock cycles (clk hposc ) depending on the settings of the field sdmpos in register sdmclkcfgfp ( table 3 . 24) . t he 4 mhz clock used to generate the chop clock (clk chopbase ) is delayed relative to the 4 mhz clock used for the digital logic (clk sdmbase ) by zero to four 20 mhz clock cycles depending on th e settings of field sdmpos2 and field sdmpos in register sdmclkcfgfp . the delay in the number of 20 mhz clock cycles of the chop clock relative to the sdm clock can be calculated using the following formula: 5 mod ) ( delay sdmpos sdmpos2 - = ( 6 ) important: the delay programmed into field sdmpos2 is related to clk muxclk , not to clk sdmbase . table 3 . 22 shows the value that must be programmed into field sdmpos2 depending on the field sdmpos and the desired delay. table 3 . 22 value for sdmpos2 depending on sdmpos and desired clock delay from sdm to chop clock delay sdmpos 2 sdmpos = 0 sdmpos = 1 sdmpos= 2 sdmpos= 3 0 0 1 2 3 1 1 2 3 4 2 2 3 4 0 3 3 4 0 1 4 4 0 1 2
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 66 april 20, 2016 figure 3 . 13 fp adc clocking scheme for sdmpos = sdmpos2 = 2; sdmclkdivfp = 1; sdmchopclkdiv = 0 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 clk hposc clk muxclk clk sdmbase clk chopbase sdm clock chop clock cnt figure 3 . 14 fp adc clocking for sdmpos = 1 and sdmpos2 = 4; sdmclkdivfp = 1; sdmchopclkdiv = 0 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 clk hposc clk muxclk clk sdmbase clk chopbase sdm clock chop clock cnt
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 67 april 20, 2016 figure 3 . 15 fp adc clocking for sdmpos = 3 and sdmpos2 = 0; sdmclkdivfp = 1; sdmchopclkdiv = 0 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 clk hposc clk muxclk clk sdmbase clk chopbase sdm clock chop clock cnt figure 3 . 16 fp adc clocking for sdmpos = 0 and sdmpos2 = 3; sdmclkdivfp = 1; sdmchopclkdiv = 0 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 clk hposc clk muxclk clk sdmbase clk chopbase sdm clock chop clock cnt 3.8.1.2 adc clocks in the lp/ ulp state in the lp or ulp s tate, the sdm clock is generated from the 125 khz clock (clk lposc ) by dividing it by two times the value programmed into register sdmclkdivlp (see table 3 . 23) : khz 125 f ; 2 f f lp lp sdm = ? = p s d mcl k di v l ( 7 ) important : when sdmclkdivlp is set to 0, the frequency of the sdm clock is 62.5 khz .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 68 april 20, 2016 the chop clock is generated from the sdm clock by further dividing it by 2, 4, 8 , or 16 depending on the setting of the sdmchopclkdiv field in register adcgomd: 1) ( sdm chop 2 f f + - ? = div sdmchopclk ( 8 ) both the smd and chop clocks are generated from the same 125 khz clock that is used for the digital logic. shifting of the clocks used to generate the sdm and chop clock is not possible and not needed as the analog clocks are generated on the falling clock edge where the digital logic is already stable and will not influence the analog section . figure 3 . 17 lp/ ulp adc clocking scheme; sdmclkdivl p = 5; sdmchopclkdiv = 0 clk lposc sdm clock chop clock 3.8.1.3 register ?sdmclkcfglp? ? configuration re gister for the sdm clocks in the lp/ ulp state table 3 . 23 register sdmclkcfglp name address bits default access description sdmclkdivlp[7:0] b0 hex [7:0] 18 hex rw c lock divider value for the sdm clock in the lp and ulp s tate s related to the 125khz base clock . with sdmclkdivlp = 0, the divider value is 2 . sdmclkdivlp[9:8] b1 hex [1:0] 0 0 bin rw u nused [7:2] 00 0 0 00 bin ro u nused; always write as 0 . 3.8.1.4 register ?sdmclkcfgfp? ? configuration register for the sdm clocks in the fp state table 3 . 24 register sdmclkcfgfp name address bits default access description sdmclkdivfp[7:0] b2 hex [7:0] 0 8 hex rw c lock divider value for the sdm clock in the fp s tate related to the 4mhz base clock f hp. if 0, then the sdm clock is 2mhz. sdmclkdivfp[9:8] b3 hex [1:0] 00 bin rw u nused [2] 0 bin ro u nused; always write as 0 sdmpos2 [5:3] 010 bin rw p osition of the chop clock ( clk chopbase ) relat ive to the base clock clk muxclk (possible values = 0 to 4) sdmpos [7:6] 10 bin rw p osition of the sdm clock ( clk sdmbase ) relat ive to the base clock clk muxclk
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 69 april 20, 2016 3.8.2 adc data path the incoming 2 nd and 3 rd order bit streams from the analog part of the sd - adcs are first captured and then driven through a 3 rd order noise shaping filter as illustrated in figure 3 . 18 . the digital conversion is accomplished by a 4 th order low - pass filter (sinc 4 decimation filter). the bit stream capturing and the noise shaping filter cannot be directly changed by the user (no configurat ion registers), but the selected oversampling rate ( adcsamp register field osr ) affects the sinc 4 decimation filter (one output value per n input values). figure 3 . 18 functional b lock d iagram of the d igital adc d ata p ath bitstream capture noise cancellation sinc 4 decimation filter post filter {000, bist bitstream} 4 4 bitstream capture noise cancellation sinc 4 decimation filter post filter {000, bist bitstream} 4 4 data post correction result register sdm 1 sdm 2 a simple post filter (moving average filter) is placed behind the sinc 4 decimation filter. the user can select the averaging function (no averaging; 2 - stage averaging; or 3 - stage averaging) via the avgfiltcfg bit field in the adcsamp register (see table 3 . 56) when chopping is disabled (see section 3.8.4.4 ) . when chopping is enabled, the 2 - s tage averaging is used independent ly of the filter configuration. the function of the 2 - stage averaging filter is 2 ) 1 t ( x ) t ( x ) t ( x in in out - + = ( 9 ) the function of the 3 - stage averaging filter is 4 ) 2 t ( x ) 1 t ( x 2 ) t ( x ) t ( x in in in out - + - ? + = ( 10) where t = current sample t - 1 = previous sample t - 2 = sample before previous sample, etc .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 70 april 20, 2016 3.8.2.1 data post - correction block the data post - correction block performs the offset and gain correction of the post - filtered conversion data as well as the over - range and the overflow detection. figure 3 . 19 data post correction post-filter channel 1 post-filter channel 2 + x adctoff adcvoff adccoff adccgan adcvgan adctgan x curpocogain voltpocogain temppocogain over-range check overflow check first, an over - range check is performed on the incoming data. values that are outside the interval [ - 0.75; 0.75) are always mapped to the corresponding interval boundary. this is done for better results as the adc accuracy decreases for large input values. t he user can enable a ?set interrupt? strobe for each of the two channel s by setting the adcacmp register bits covrena and vtovrena to 1 (see table 3 . 54) . note: the ?set interrupt? strobes go to the interrupt controller. they have a different meaning than the corres - ponding ?interrupt enable? bits (interrupt bits [15:14] in the irqena registe r) . the ?set interrupt? bits are used to select whether the interrupt status bits will be set or not ; the ?interrupt enable? bits select whether the interrupt status bits will drive the interrupt line or not. after the over - range check, a programmable offs et, interpreted as a number in the range [ - 1.0; 1.0), is added to the data. three registers allow setting different offsets for current, voltage, and temperature: adccoff , adcvoff , and adctoff (see table 3 . 25 , table 3 . 27 , and table 3 . 29 respectively). the offset correction is followed by two multiplication stages. in the first multiplication stage, individual gain factors for current ( adccgan ), voltage ( adcvgan) , or temperature ( adctgan ), interpreted as numbers in the range [0.0; 2.0), are multiplied by the offset corrected data (see table 3 . 26, table 3 . 28 , and table 3 . 30 respectively) . the second multiplication stage is used to shift the significant data into the most significant bits of the result register. the data is multiplied by 1, 2, 4 , or 8, which can be individually selected for current, voltage , and temperature via the curpocogain, voltpocogain , and temppocogain fields in the adcpocogain register (see table 3 . 31) .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 71 april 20, 2016 figure 3 . 20 data representation through data post correction including over - r ange and overflow levels note: the yellow area represents the us able data space to avoid overflow when the post correction gain is 2. 7fffff hex 400000 hex 000000 hex 800000 hex c00000 hex a00000 hex 600000 hex 1 2.4v 3/4 1.8v 1/2 1.2v 0 0.0v -1 -2.4v -3/4 -1.8v -1/2 -1.2v ffffff hex e00000 hex c00000 hex 800000 hex 400000 hex 200000 hex 000000 hex 7fffff hex 400000 hex 000000 hex 800000 hex c00000 hex a00000 hex 600000 hex over-range over-range unsigned signed overflow overflow signed pocogain = 2 input to data post-correction gain and offset correction post-correction an overflow check is performed on the output of the second multiplication stage as the result might be out of the representable range of [ - 1.0; 1.0). t he user can also enable a ?set interrupt? strobe for each of the two channels by setting the adcacmp register bits covrena and /or vtovrena to 1 (same bits as for the over - range check) . note: although the same ?set interrupt strobe enable? bit is used for o ver - range and overflow, independent interrupt status bits can be individually enabled or disabled.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 72 april 20, 2016 figure 3 . 21 illustrates the common enable covrena f or the interrupt strobes for current over - range and overflow. the function of vtovrena as the common enable for the interrupt strobes for voltage/temperature over - range and overflow conditions is similar. figure 3 . 21 common e nable for the ?set overrange? and ?set overflow? i nterrupt s trobes for c urrent irqstat[12] (current overflow) covrena & irqstat[14] (current overrange) & current overflow detected set interrupt current overrange detected set interrupt 3.8.2.2 register ?adccoff? ? offset correction value for current channel table 3 . 25 register adccoff name address bits default access description adccoff[7:0] 33 hex [7:0] 00 hex rw offset value for current value; interpreted as a number in the range [ - 1.0; 1.0) formatted in 2?s complement representation . programmable offset range = +/ - 2 v ref ; v ref = full - scale range adc . note: the initial value is loaded from otp after reset . adccoff[15:8] 34 hex [7:0] 00 hex rw adccoff[23:16] 35 hex [7:0] 00 hex rw 3.8.2.3 register ?adccgan? ? gain correction value for current channel table 3 . 26 register adccgan name address bits default access description adccgan[7:0] 30 hex [7:0] 00 hex rw gain value for current value; interpreted as a number in the range [0.0; 2.0) . note: the initial value is loaded from otp after reset . adccgan[15:8] 31 hex [7:0] 00 hex rw adccgan[23:16] 32 hex [7:0] 80 hex rw 3.8.2.4 register ?adcvoff? ? offset correction value for voltage channel table 3 . 27 register adcvoff name address bits default access description adcvoff[7:0] 39 hex [7:0] 00 hex rw offset value for voltage value; interpreted as a number in the range [ - 1.0; 1.0) formatted in 2?s complement representation. programmable offset range = +/ - 2 v ref ; v ref = full - scale range adc . note: the initial value is loaded from otp after reset. adcvoff[15:8] 3a hex [7:0] 00 hex rw adcvoff[23:16] 3b hex [7:0] 00 hex rw
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 73 april 20, 2016 3.8.2.5 register ?adcvgan? ? gain correction value for voltage channel table 3 . 28 register adcvgan name address bits default access description adcvgan[7:0] 36 hex [7:0] 00 hex rw gain value for voltage value; interpreted as a number in the range [0.0; 2.0) note: the initial value is loaded from otp after reset. adcvgan[15:8] 37 hex [7:0] 00 hex rw adcvgan[23:16] 38 hex [7:0] 80 hex rw 3.8.2.6 register ?adctoff? ? offset correction value for temperature channel table 3 . 29 register adctoff name address bits default access description adctoff[7:0] 3e hex [7:0] 00 hex rw offset value for temperature value; interpreted as a number in the range [ - 1.0; 1.0) note: the initial value is loaded from otp after reset. adctoff[15:8] 3f hex [7:0] 00 hex rw 3.8.2.7 register ?adctgan? ? gain correction value for temperature channel table 3 . 30 register adctgan name address bits default access description adctgan[7:0] 3c hex [7:0] 00 hex rw g ain value for temperature value; interpreted as a number in the range [0.0; 2.0) note: the initial value is loaded from otp after reset . adctgan[15:8] 3d hex [7:0] 80 hex rw
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 74 april 20, 2016 3.8.2.8 register ?adcpocogain? ? post correction gain configuration table 3 . 31 register adcpocogain name address bits default access description curpocogain 57 hex [1:0] 0 0 bin rw p ost correction gain for the current channel : 0 g ain factor is 1 1 g ain factor is 2 2 g ain factor is 4 3 g ain factor is 8 voltpocogain [3:2] 0 0 bin rw p ost correction gain for the voltage channel : 0 g ain factor is 1 1 g ain factor is 2 2 g ain factor is 4 3 g ain factor is 8 temppocogain [5:4] 0 0 bin rw p ost correction gain for the temperature channel : 0 g ain factor is 1 1 g ain factor is 2 2 g ain factor is 4 3 g ain factor is 8 u nused [7:6] 0 0 bin ro u nused; always write as 0 . 3.8.3 adc operating modes and result registers 3.8.3.1 single measurement results each value coming from the data post - correction block is the result of a single measurement. these values are signed and stored in the corresponding result registers adccdat, adcvdat, adctdat , or adcrdat (see table 3 . 32 through table 3 . 35). the following formulas can be used to calculate the battery current and the battery voltage from t he result register values: g g 2 r v 2 i poco ana 23 shunt ref bat ? ? ? ? ? = adccdat ( 11) g 2 v 2 24 v poco 23 ref bat ? ? ? ? = adcvdat ( 12) where : i bat b attery current v bat b attery voltage g ana a nalog gain in current path ( pgaifc ? pga1 ? pga2 ; see table 3 . 36 ) g poco digital gain in post - correction stage (second multiplication ; see table 3 . 31) r shunt s hunt resistance v ref r eference voltage adccdat r egister value for current adcvdat r egister value for voltage
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 75 april 20, 2016 3.8.3.2 register ?adccdat? ? single current measurement value table 3 . 32 register adccdat name address bits default access description adccdat[7:0] 02 hex [7:0] 00 hex ro c onversion result of a single current measurement (signed value) adccdat[15:8] 03 hex [7:0] 00 hex ro adccdat[23:16] 04 hex [7:0] 00 hex ro 3.8.3.3 register ?adcvdat? ? single voltage measurement value table 3 . 33 register adcvdat name address bits default access description adcvdat[7:0] 05 hex [7:0] 00 hex ro c onversion result of a single voltage measurement (signed value) adcvdat[15:8] 06 hex [7:0] 00 hex ro adcvdat[23:16] 07 hex [7:0] 00 hex ro 3.8.3.4 registers ?adctdat? and ?adcrdat? ? single temperature measurement values table 3 . 34 register adctdat name address bits default access description adctdat[7:0] 0a hex [7:0] 00 hex ro c onversion result of a single temperature value (signed value; inverted); this value is either the internally measured temperature or the ntc value of an external temperature measurement . important : t his value is sign - inverted . adctdat[15:8] 0b hex [7:0] 00 hex ro table 3 . 35 register adcrdat name address bits default access description adcrdat[7:0] 08 hex [7:0] 00 hex ro c onversion result of a single temperature measurement by reading a voltage across the reference resistor (external temperature measurement only). adcrdat[15:8] 09 hex [7:0] 00 hex ro
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 76 april 20, 2016 3.8.3.5 register ?adcgain? ? analog gain configuration in the current path table 3 . 36 register adcgain name address bits default access description pgaifc 52 hex [1:0] 0 0 bin rw s ets the gain of the pa - c preamplifier in the analog current path : 0 gain factor is 1 1 gain factor is 2 2 gain factor is 4 3 gain factor is 8 pga1 [3:2] 0 0 bin rw s ets the gain of the pga - 1 programmable gain amplifier in the analog current path : 0 gain factor is 1 1 gain factor is 2 2 gain factor is 4 3 gain factor is 8 pga2 [4] 0 bin rw s ets the gain of pga - 2 programmable gain amplifier in the analog current path : 0 gain factor is 4 1 gain factor is 8 u nused [7:5] 0 0 0 bin ro u nused; always write as 0 . 3.8.3.6 result counter functionality and conversion ready strobes three status bits are available in the interrupt status ( irqstat[7:5]) that signal that the conversion of current, voltage , or temperature has been completed. the ?set interrupt? strobe is generated for each completed temperature measurement. for the voltage and current measurements, the user can independently select whether the corresponding ?set interrupt? strobe will be generated after each single measurement (srcs ? single result count sequence) or after n measurements (mrcs ? multi - result count sequence). the register adccrcl configures the number of current measurements befo re the current conversion ready strobe is generated ; the maximum number is 65535 (see table 3 . 37) . setting this register to 0 disables the result coun t functionality , which means that srcs is configured. the p resent result counter value can always be read from the register adccrcv (see table 3 . 38 ). the result counter is reset when the bit field startadcc in register adcct rl is set (rising edge) in the fp s tate (see table 3 . 58) or at the start of the first measurement in lp / ulp s tate. it is set to 1 at the end of the first measurement after the limit defined in adccrcl has been reached. the register adcvrcl configures the number of measurements before the voltage conversion ready strobe is generated, the maximum number is 15 (see table 3 . 39) . setting thi s register to 0 disables the result count functionality , which means that srcs is configured. the p resent result counter value can always be read from the register adcvrcv (see table 3 . 40 ). the result counter is reset when startadcv in register adcctrl is set (rising edge) in the fp s tate or at the start of the first measurement in the lp/ ulp s tate. it is set to 1 at the end of the first measurement after the limit defined in adcvrcl was reached. note: setting register adccrcl or adcvrcl to 1 also leads to src s in the corresponding channel.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 77 april 20, 2016 3.8.3.7 register ?adccrcl? ? current result count limit table 3 . 37 register adccrcl name address bits default access description adccrcl[7:0] 40 hex [7:0] 00 hex rw n umber of current measurements before the current conversion ready strobe is generated . note: setting this bit to 0 disables this functionality , and the strobe is generated after each current measurement . adccrcl[15:8] 41 hex [7:0] 0 0 hex rw 3.8.3.8 register ?adccrcv? ? current result count value table 3 . 38 register adccrcv name address bits default access description adccrcv[7:0] 1b hex [7:0] 0 0 hex ro present value of the current result counter . adccrcv[15:8] 1c hex [7:0] 0 0 hex ro 3.8.3.9 register ?adcvrcl? ? voltage result count limit table 3 . 39 register adcvrcl name address bits default access description adcvrcl 45 hex [3:0] 0000 bin rw n umber of voltage measurements before the voltage conversion ready strobe is generated . note: setting this bit to 0 disables this functionality , and the strobe is generated after each voltage measurement . u nused [7:4] 0000 bin ro u nused; always write as 0 . 3.8.3.10 register ?adcvrcv? ? voltage result count value table 3 . 40 register adcvrcv name address bits default access description adcvrcv 1e hex [3:0] 0000 bin ro present value of the voltage result counter. unused [7:4] 0000 bin ro unused; always write as 0.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 78 april 20, 2016 3.8.3.11 current threshold comparator functionality the current threshold comparator functionality is used to monitor the current level and to generate an interrupt ( irqstat[8] ) if the absolute current value exceeds a programmable limit for a configurable number of conversion results. this functionality is enabled if the field ctcvmode in register adcacmp is set to a non - zero valu e (see table 3 . 54 table 3 . 58) . if enabled, this function is always triggered when a new cu rrent value is measured. the absolute value of the most significant 17 bits of the measured current value is compared to the expanded programmable threshold register adccrth (see table 3 . 41) : [ ] ( ) { } adccr t h adccdat , 0 7 : 23 abs ( 13) when the current threshold comparator functionality is enabled, the current threshold counter is used to count the number of conversions where the absolute current value is above the threshold. if the absolute current value is greater than or equal to the programmed threshold (above formula is true), the internal current threshold counter is incremented (until it reaches its maximum value ff hex ). otherwise the counter is either decremented ( if ctcvmode field in register adcacmp set to 1) or reset ( if ctcvmode set to 2) , or it remains unchanged ( if ctcvmode set to 3). the p resent value of the current threshold counter can be read from the register adcctcv (see table 3 . 43). note: when bit field ctcvmode in r egister adcacmp is set to 00 bin , the current threshold comparator function - ality is disabled and register adccrtv is always 0. note: when ctcvmode is set t o 0 1 bin , the current threshold counter is not decremented when the counter is 0. after each comparison of the absolute current value versus the current threshold level and after the current threshold counter has been updated, the internal current threshold counter is compared to the current threshold counter limit (register adcctcl ; see table 3 . 42 ). whenever the current threshold counter is greater than or equal to the programmable limit, a ?set interrupt? strobe is generated. note: when the current threshold counter has reached its li mit and it is configured to keep its value if the limit is not reached, a ?set interrupt? strobe is generated for each new measurement even if the new value is below threshold. the current threshold counter is reset to 0 for the following conditions: ? if ctcvmode is set to 2 and the absolute current value is below t he programmed threshold adccrth ? on assertion of startadcc (rising edge) in the fp s tate ? at the start of the first conversion in the lp or ulp s tate ? each time the result counter is reset (if the re sult counter is enabled) and the current threshold counter reset mode bit (bit ctcvrstmode in register adcacmp ) is set to 1
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 79 april 20, 2016 3.8.3.12 register ?adccrth? ? absolute current threshold table 3 . 41 register adccrth name address bits default access description adccrth[7:0] 42 hex [7:0] 00 hex rw a bsolute current threshold (unsigned value) . when using current comparator threshold functionality, the absolute current value is compared to {0, adccrth}. adccrth[15:8] 43 hex [7:0] 00 hex rw 3.8.3.13 register ?adcctcl? ? current threshold counter limit table 3 . 42 register adcctcl name address bits default access description adcctcl 44 hex [7:0] 00 hex rw c urrent threshold counter limit . this register defines the number of current measurements that must be greater than or equal to the threshold adccrth before the interrupt is set. 3.8.3.14 register ?adcctcv? ? current threshold counter value table 3 . 43 register adcctcv name address bits default access description adcctcv 1d hex [7:0] 00 hex ro present current threshold counter value . 3.8.3.15 current accumulator functionality the current accumulator functionality is used to sum up all current conversion results. the present accumulator value can be read from the register adccaccu (signed value ; see table 3 . 45 ). positive conversion results increment the accumulator registe r, negative conversion results decrement it. the accumulator register saturates at its minimum and maximum value. the current accumulator is reset to 0 under these conditions : ? on assertion of startadcc (rising edge) in the fp s tate ? at the start of the first conversion in the lp or ulp s tate ? each time the result counter is reset (if the result counter is enabled) and the current accumulator reset mode bit (bit accurstmode in register adcacmp ) is set to 1 note: the current accumulator functio nality can be used to calculate the mean value of the current.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 80 april 20, 2016 the current accumulator is also compared to a programmable signed accumulator threshold value (register adccaccth ). this comparison can be used to generate a ?set interrupt? strobe for irqstat[11] ; however, to enable the generation of the ?set interrupt? strobe, bit caccuthena in register adcacmp must be set to 1 (see table 3 . 54 ) . the ?set in terrupt? strobe is always generated on update of the accumulator register when ? adccaccth is greater than 0 and adccaccu is greater than adccaccth ? adccaccth is lower than 0 and adccaccu is lower than adccaccth ? adccaccth is equal to 0 and adccaccu is not equal to 0 3.8.3.16 register ?adccaccth? ? current accumulator threshold value table 3 . 44 register adccaccth name address bits default acces s description adccaccth[7:0] 48 hex [7:0] 00 hex rw s igned threshold value for current accumulator mode adccaccth[15:8] 49 hex [7:0] 00 hex rw adccaccth[23:16] 4a hex [7:0] 00 hex rw adccaccth[31:24] 4b hex [7:0] 00 hex rw 3.8.3.17 register ?adccaccu? ? current accumulator value table 3 . 45 register adccaccu name address bits default access description adccaccu[7:0] 0c hex [7:0] 00 hex ro present current accumulator value adccaccu[15:8] 0d hex [7:0] 00 hex ro adccaccu[23:16] 0e hex [7:0] 00 hex ro adccaccu[31:24] 0f hex [7:0] 00 hex ro 3.8.3.18 voltage threshold comparator and voltage accumulator functionality the zssc1750/51 also provides a threshold comparator as well as an accumulator comparator for the battery voltage channel but with reduced functionality. if the vthsel bit in register adcacmp is set to 0, the absolute value of the most significant 17 bits of a single voltage measurement (register adcvdat) is compared to the programmable voltage threshold (register adcvth ; see table 3 . 46 ). in this case, register adcvth is interpreted as an unsigned value . there is also no counter functionality. whenever the absolute voltage value is below the programmed threshold, a ?set interrupt? strobe for irqstat[9] i s generated if the strobe generation is enabled ( the field vthwuena in register adcacmp is set to 1). [ ] ( ) { } adcvth adcvdat , 0 7 : 23 abs < ( 14) when bit vthsel in register adcacmp is set to 1, the voltage accumulator functionality is enabled. t he voltage result counter functionality must also be enabled ( register adcvrcl > 0). the voltage accumulator functionality is used to sum up all voltage conversion results. in contrast to the current channel, only the upper 20 bits of the voltage conversion results are accumulated. the p resent accumulator value can be read from the register adcvaccu (signed value ; see table 3 . 47 ). positive conversion results increment the accumulator register ; neg - ative conversion results decrement it. the accumulator register saturates at its minimum and maximum value.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 81 april 20, 2016 the voltage a ccumulator is reset to 0 under these conditions : ? on assertion of startadcv (rising edge) in the fp s tate ? at start of the fir st conversion in the lp or ulp s tate ? each time the result counter is reset (if the result counter is enabled) note: the voltage accu mulator functionality can be used to calculate the mean value of the voltage. after the last accumulation within an mrcs, the upper 16 bits of the voltage accumulator are compared to the voltage threshold adcvth, which is interpreted as a signed value in t his case. this comparison can be used to generate a ?set interrupt? strobe for irqstat[9]; however, to enable the generation of the ?set interrupt? strobe, bit vthwuena in register adcacmp must be set to 1. the ?set interrupt? strobe is generated when ? adcvth is greater than 0 and adcvaccu is less than or equal to adcvth ? adcvth is lower than 0 and adcvaccu is greater than or equal to adcvth ? adcvth is equal to 0 and adcvaccu is equal to 0 important: the threshold adcvth is either interpreted as an unsigned or signed value depending on the operation mode ( vthsel). note: t he voltage comparators compare only on the msb s of the conversion result, so it migh t be beneficial to use the post - correction gain functionality to shift left the results to increase the accur acy of the comparison. 3.8.3.19 register ?adcvth? ? voltage threshold value table 3 . 46 register adcvth name address bits default access description adcvth[7:0] 46 hex [7:0] 00 hex rw v oltage threshold . if vthsel == 0 , then adcvth is interpreted as an unsigned value and it is compared to the absolute value of a single voltage conversion . if vthsel == 1 , then adcvth is interpreted as a signed value and it is compared to the accumu - lated voltage conversion results at the end of an mrcs . adcvth[15:8] 47 hex [7:0] 00 hex rw 3.8.3.20 register ?adcvaccu? ? voltage accumulator value table 3 . 47 register adcvaccu name address bits default access description adcvaccu[7:0] 10 hex [7:0] 00 hex ro present voltage accumulator value adcvaccu[15:8] 11 hex [7:0] 00 hex ro adcvaccu[23:16] 12 hex [7:0] 00 hex ro
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 82 april 20, 2016 3.8.3.21 minimum and maximum values of current and voltage for current and voltage measurements, the minimum and maximum values are determined on the upper 16 bits of the corresponding conversion results. these values can be read from registers adccmax, adccmin , adcvmax, and adcvmin . these registers are reset in t he same manner as the corresponding accumulator registers. these values are only provided for statistical reasons and can be used to assess the accumulated current or voltage values when used for mean value calculation. note: as the minimum and maximum val ues are only determined on the 16 msbs of the corresponding con - version results, it might be beneficial to use the post correction gain functionality to shift left the results to increase the accuracy of the comparison. 3.8.3.22 register ?adccmax? ? maximum current value table 3 . 48 register adccmax name address bits default access description adccmax[7:0] 13 hex [7:0] 00 hex ro u pper 16 bits of the maximum measured current value (signed value) adccmax[15:8] 14 hex [7:0] 80 hex ro 3.8.3.23 register ?adccmin? ? minimum current value table 3 . 49 register adccmin name address bits default access description adccmin[7:0] 15 hex [7:0] ff hex ro u pper 16 bits of the minimum measured current value (signed value) adccmin[15:8] 16 hex [7:0] 7f hex ro 3.8.3.24 register ?adcvmax? ? maximum voltage value table 3 . 50 register adcvmax name address bits default access description adcvmax[7:0] 17 hex [7:0] 00 hex ro u pper 16 bits of the maximum measured voltage value (signed value) adcvmax[15:8] 18 hex [7:0] 80 hex ro 3.8.3.25 register ?adcvmin? ? minimum voltage value table 3 . 51 register adcvmin name address bits default access description adcvmin[7:0] 19 hex [7:0] ff hex ro u pper 16 bits of the minimum measured voltage value (signed value) adcvmin[15:8] 1a hex [7:0] 7f hex ro
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 83 april 20, 2016 3.8.3.26 temperature limits the user can define an upper (register adctmax ) and a lower (register adctmin ) limit for the external and internal temperature measurement. on each update of register adctdat (see table 3 . 34 ), the upper 8 bits are compared to the signed limit values. this can be used to generate a ?set interrupt? strobe for irqstat[10] if the value for adctdat is outside the interval [ adctmin ; adctmax] and the twuena bit in register adcacmp is set to 1 (see table 3 . 54 ) . note: t he minimum and maximum values are only compared to the 8 msbs of the con version result, so it might be beneficial to use the post correction gain functionality to shift left the results to increase the accuracy of the comparison. important: t he value stored in register adctdat is inverted : the value given in register adctmax is the value for the lower temperature interrupt threshold and the value given in register adctmin is the va lue for the higher temperature interrupt threshold . 3.8.3.27 register ?adctmax? ? upper boundary for temperature interval table 3 . 52 register adctmax name address bits default access description adctmax 4c hex [7:0] 00 hex rw lower boundary for the temperature interval compared to the upper bits of adctdat . 3.8.3.28 register ?adctmin? ? lower boundary for temperature interval table 3 . 53 register adctmin name address bits default access description adctmin 4d hex [7:0] 00 hex rw upper boundary for the temperature interval compared to the upper bits of adctdat . 3.8.3.29 miscellaneous registers the registers defined in the next three sections provide settings that enable interrupts or control various functions related to the adcs.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 84 april 20, 2016 3.8.3.30 register ?adcacmp? ? adc function enable register table 3 . 54 register adcacmp name address bits default access description anagndsw 4e hex [0] 0 bin rw if set to 1, the signal pdexttemp (see figure 3 . 12 ), which is normally controlled by the pmu, is forced to 1. in this case, the transistor shown in figure 3 . 12 is not conducting. ctcvmode [2:1] 0 0 bin rw c urrent threshold comparator mode : 0 the current threshold c omparator m ode is disabled. 1 adcctcv is decremented when the absolute current value is below the threshold and incremented otherwise. 2 adcctcv is reset when the absolute current value is below the threshold and incremented otherwise. 3 adcctcv retains its value when the absolute current value is below the threshold and incremented otherwise. caccuthena [3] 0 bin rw if set to 1, enables the strobe to interrupt the controller when the current accumulator exceeds its threshold . covrena [4] 1 bin rw if set to 1, enables the strobes to interrupt the controller when an over - range or overflow has been detected in the current channel . vtovrena [5] 1 bin rw if set to 1, enables the strobes to interrupt the controller when an over - range or overflow has been detected in the voltage/ temperature channel . ctcvrstmode [6] 0 bin rw if set to 1, then adcctcv is reset when the current result counter is reset ( adccrcv ) . accurstmode [7] 0 bin rw if set to 1, then adccaccu is reset when the current result counter is reset ( adccrcv ) . vthwuena 4f hex [0] 0 bin rw if set to 1, enables the strobe to interrupt the controller for the voltage threshold comparator and voltage accumulator functionality . vthsel [1] 0 bin rw if set to 0 , the absolute value of the single voltage conversion result is compared to the threshold adcvth. if set to 1 , the accumulated results of all voltage conversions within an mrcs are compared to the threshold adcvth . twuena [2] 0 bin rw if set to 1, enables the strobe to interrupt the controller for check ing the temperature limits . u nused [7:3] 0 0 000 bin ro u nused; always write as 0 .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 85 april 20, 2016 3.8.3.31 register ?adcgomd? ? reference voltage and sdm configuration table 3 . 55 register adcgomd name address bits default access description vrefsel 50 hex [1:0] 0 0 bin rw s election of the voltage reference : 0 vbgh (high precision bandgap) 1 vbgl (low power bandgap) 2 vcm (common mode voltage) 3 external reference voltage sdmchopclkdiv [3:2] 00 bin rw c lock divider value for the chop clock related to the sdm clock . see equation ( 5 ) in section 3.8.1.1 for the fp s tate and equation ( 8 ) in section 3.8.1.2 for the lp/ulp s tate. sdmsetup [7:4] 0 00 1 bin rw c onfiguration of the initial setup procedure : 0 execute 4 sdm clock cycles 1 execute 8 sdm clock cycles ? 7 execute 512 sdm clock cycles 8 - 15 execute 1024 sdm clock cycles 3.8.3.32 register ?adcsamp? ? oversampling and filter configuration table 3 . 56 register adcsamp name address bits default access description osr 51 hex [1:0] 00 bin rw o versampling rate : 0 256x oversampling 1 128x oversampling 2 64x oversampling 3 32x oversampling u nused [2] 0 bin ro u nused; always write as 0 . avgfiltcfg [4:3] 00 bin rw c onfiguration of post filter (averaging filter) : 0 - 1 no averaging 2 2 - stage averaging filter 3 3 - stage averaging filter choppause [5] 0 bin rw l ength of pause in chopping mode : 0 8 sdm clock cycles 1 16 sdm clock cycles u nused [7:6] 00 bin ro u nused; always write as 0 .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 86 april 20, 2016 3.8.4 adc control and conversion timing in the fp s tate, the adc unit is running with the 4 mhz clock derived from the hp oscillator. its operation can be fully controlled by the external microcontroller via register settings. in the lp or ulp s tate, the adc unit is running with the 125 khz clock from the lp oscillator. b asic configurations for the adc unit are taken from the register file ; however, its operation is fully controlled by the pmu. 3.8.4.1 adc operation in the fp state before any of the adcs can be used in the fp s tate, they must be powered up by setting the pwradci bit for the current adc and/or the pwradcv bit for the voltage/temperature adc in the pwrcfgfp register to 1 (see table 3 . 18) . these bits can be kept set to 1 when entering one of the power - down states as the pmu takes over the control of the power signals. the user can select which kind of operation will be perfor med by the adcs and can control the input multiplexers shown in figure 3 . 12 by setting the field adcmode in the adcctrl register appropriately (see table 3 . 58 ) . the following settings are possible: table 3 . 57 adcmode s ettings adcmode c urrent adc c onfiguration v oltage / t emperature adc c onfiguration 0 c urrent v oltage inp/ inn d ivided vbat/ vssa 1 c urrent e xternal temperature in p/ inn vdda/nth and nth/ ntl 2 c urrent i nternal temperature inp/ inn vptat/ vref 3 offset calibration m ode; shortened inputs vcm/ vcm vcm/ vcm 4 gain calibration m ode @ maximum (positive) input vref / vssa 1) vref/ vssa 5 gain calibration m ode @ minimum (negative) input vssa / vref 1) vssa / vref 6 1 mv internal test voltage v oltage 1 mv/ vssa divided vbat/ vssa 7 test m ode; each multiplexer is individually controlled by the following: csel field in adcchan register ( table 3 . 59 ) vtsel field in adcchan register 1) the two g ain c alibration m odes cause an adc over - range error in the current adc as the minimum gain of pga2 is 4. therefore these modes are not usable for the current adc. after setting the desired mode of operation, the user must start the conversion by setting the startadcc bit in the adcctrl register (see table 3 . 58) for the current channel and/or the startadcv bit for the voltage/ temperature channel to 1. after an initial setup phase, measurement results are stored in the corresponding result regis ters. by controlling the startadc bits, the user is able to generate an individual conversion sequence (adc operation stops after one conversion sequence has finished) or continuous conversion (adc operation continues after one conversion sequence has fini shed).
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 87 april 20, 2016 a conversion sequence is defined as a series of several measurements. the number of measurements to be performed is controlled by the result counter functionality , so it is possible to have multiple measurements per conversion sequence (mrcs) or jus t a single measurement (srcs). at the end of one conversion sequence, the ?set interrupt? strobe for the corresponding conversion interrupt ready status bit ( irqstat[7:5] ) is generated. although this strobe is only generated after the last measurement with in an mrcs, each measurement in the mrcs is used for accumulation and min imum /max imum determination. note: the mrcs functionality is only available for current and voltage measurements , not for temperature measurements. to perform an individual conversion sequence for a srcs or mrcs, the user must generate a strobe signal on the corresponding startadc bit by setting the startadc bit to 1 (rising edge) first and then to 0 (falling edge). the rising edge of startadc signals the adc to start the conversion. on this start signal , the corresponding adcactive flag is set to 1 , which can be read from bits 4 and 5 in the ssw (see section 3.1.1 ) . when the conv ersion sequence has finished, the corresponding ready signal is generated. at that time, the internal logic evaluates the status of the startadc bit again. if it was cleared already as required for an individual conversion sequence, the adc stops its opera tion and clears the adcactive flag. this behavior is shown in figure 3 . 22 and figure 3 . 23 . figure 3 . 22 individual srcs startadc adcactive result ready a s etup t ime and s ingle m easurement note that the adc stops since startadc is low at the end of the conversion sequence for the individual srcs. figure 3 . 23 individual mrcs ( example for r esult c ounter of 3) startadc adcactive result ready a setup time and single measurement b c single measurement note that the adc stops since startadc is low at the end of the conversion sequence for an individual mrcs . important: t he ready strobe shown in figure 3 . 22 and figure 3 . 23 is used to set the interrupt status bit , but the interrupt status bit remains set until it is cleared by the user?s software.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 88 april 20, 2016 to perform a continuous conversion sequence for srcs or mrcs, the user must set the corresponding startadc bit to 1 (rising edge). the rising edge of startadc signals the adc to start the conversion. on this start signal , the corresponding adcactive flag is set to 1 , which can be read from bits 4 and 5 in the ssw . when one conversion sequence has finished, the corresponding ready signal is generated. at that time, the internal logic evaluates the status of the startadc bit again. as the startadc bit is still 1, the adc continues its operation but without the need for the setup time. this behavior is shown in figure 3 . 24 and figure 3 . 25 . figure 3 . 24 continuous srcs startadc adcactive result ready a setup time and single measurement b c single measurement d note that the adc continues since startadc is high at the end of the conversion sequence for a continuous srcs . figure 3 . 25 continuous mrcs ( example for r esult c ounter of 3) startadc adcactive result ready a s etup t ime and s ingle m easurement b c s ingle m easurement g d e f note that the adc continues since startadc is high at the end of the conversion sequence for a continuous mrcs . when a continuous conversion sequence is performed that will be stopped after the p resent active conversion sequence has completed, the user only needs to clear the startadc bit of the channel that will be stopped. then the user can either wait for the nex t interrupt , which will be set by the last ready strobe , or check the corresponding adcactive bit in the ssw .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 89 april 20, 2016 figure 3 . 26 stopping c ontinuous srcs startadc adcactive result ready e f g s ingle m easurement d h i j note that the adc stops since startadc is low at the end of the conversion sequence for a continuous srcs . when a conversion sequence is performed that will be interrupted (stopped immediately), the user must clear the startadc bit of the channel that will be stopped (when set) and must set the stopadc bit in the adcctrl register to 1. in the adc unit, the stopadc bit is only evaluated when the startadc bit of a channel is low and the corresponding adcactive bit is high. figure 3 . 27 sto pping c ontinuous mrcs ( example for r esult c ounter of 3) startadc adcactive result ready c single measurement b d e f h i g note that the adc stops since startadc is low at the end of the conversion sequence for a continuous mrcs ; o therwise the stopadc bit is ignored. therefore there is only one stopadc bit that is used for both channels. this allows the user to stop both channels by clearing both startadc bits when setting the stopadc bit or to stop only one channel by keeping one startadc bit high. the signal behavior for interrupting a cha nnel is shown in figure 3 . 28 and figure 3 . 29.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 90 april 20, 2016 figure 3 . 28 interrupting a c ontinuous srcs startadc adcactive result ready e f g single measurement d h i stopadc note that the adc immediately stops since startadc is low and stopadc is high. figure 3 . 29 interrupting a c ontinuous mrcs ( example for r esult c ounter of 3) stopadc adcactive result ready c single measurement b d e f g startadc note that the adc immediately stops since startadc is low and stopadc is high. important : the stopadc bit is only evaluated when startadc bit is low. note: the interrupt sequence shown in figure 3 . 28 and figure 3 . 29 is also performed by the pmu on transition from the fp s tate to any p ower - down state as well as on transition from any power - down state to the fp s tate. this allows the user to keep the startadc bits set on transition to any power - down state. after wake - up, the adcs continue the operation they performed before going to powe r - down. most of the register settings that influence both adc channels (e.g. , oversampling rate) can only be changed when both adc channels are inactive. as explained above, this is not true for the stopadc bit. t he adcmode field can also be changed while any adc channel is active. this is useful for continuing with current measurements in the first adc channel while changing the second adc channel from voltage to temperature measurements (as an example). on the rising edge of its startadc bit, each adc cha nnel stores internally the mode it is configured for and keeps this setting until the next rising edge of its startadc bit. when one channel is reconfigured while the other one is active, this channel does not start immediately after being re - enabled but s ynchronizes to the active channel so that the results are generated at the same time. see figure 3 . 30 .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 91 april 20, 2016 figure 3 . 30 signal behavior of adcmode startadcc adcactive 1 result 1 ready 1 2 adcmode ( adc 1 ) adcmode ( reg ) startadcv adcactive 2 result 2 ready 2 adcmode ( adc 2 ) 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 0 1 2 3 4 5 6 7 8 9 0 s etup t ime + 1 m eas s etup t ime + 1 m eas s ync + s etup t ime + 1 m eas 2
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 92 april 20, 2016 3.8.4.2 register ?adcctrl? ? adc control register table 3 . 58 register adcctrl name address bits default access description startadcc 56 hex [0] 0 bin rw s tart signal for the current adc; used in the fp s tate, ignored in other states . startadcv [1] 0 bin rw s tart signal for the voltage /temperature adc; used in the fp s tate, ignored in other states . stopadc [2] 0 bin rw s top signal for both adcs; used in the fp s tate, ignored in other states . adcmode [5:3] 00 0 bin rw adc multiplexer configuration; used in the fp s tate, ignored in other states; for setting s 0, 1, 2 , and 6, the first value is applied to the current adc, the second to the voltage /temperature adc . (see section 3.8.4.1 for more details.) 0 measure current and voltage 1 measure current and external temperature 2 measure current and internal temperature 3 offset calibration 4 gain calibration @ maximum (positive) input 5 gain calibration @ minimum (negative) input 6 internal test voltage and voltage 7 test mode (control multiplexer via the adcchan register?s csel and vtsel fields) chopena [6] 0 bin rw if set to 1, chopping mode is enable d. u nused [7] 0 bin ro u nused; always write as 0 . 3.8.4.3 adc operation in lp / ulp state during the lp or ulp s tate, the adcs are fully controlled by the pmu depending on the settings of register pwrcfglp (see table 3 . 19 ). the pmu overrides the settings of the startadc bits, the stopadc bit , and adcmode field. t he settings of pwradci and pwradcv are also ignored until the system wakes up. while no further set tings are required for the continuous measurement set - ups , the user can independently configure how many current and/or voltage measurements happen within a single measurement window. for cu rrent ( the green and orange boxes in figure 3 . 6 to figure 3 . 9 ), the number of current measurements in each window is configured by the setting of adccrcl (see table 3 . 37 ). for voltage ( the orange boxes shown in figure 3 . 6 to figure 3 . 9 ), the number of vol tage measurements in each window is configured by the setting of adcvrcl (see table 3 . 39 ). there is always only one temperature measurement as the last measurement made by the voltage/temperature adc in a sample period . important: if an interrupt wakes up the system before the end of a measurement window, the conversion sequence is interrupted and less than the configured number of measuremen ts will have been completed . this can be checked by the registers adccrcv (see table 3 . 38) and adcvrcv (see table 3 . 40).
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 93 april 20, 2016 3.8.4.4 adc conversion timing the complete conversion process is controlled by an internal state machine that guarantees that only valid measurement results are used. the base for a ll adc timings is the sdm clock, which is generated from the 4 mhz clock in fp s tate or from the 125 khz clock in lp and ulp s tate. after the adc measurement has been started (rising edge of startadc ), the state machine always introduces a configurable number of sd m clock cycles (field sdmsetup in register adcgomd ; see table 3 . 55 ) to allow the analog part of the sdm to settle. after this delay, the incoming bit streams are used to fill the sinc 4 decimation filter. this lasts 4 times the sample rate , which is configured by the oversampling rate ( the osr field in register adcsamp ; see table 3 . 56) . then the first valid result value comes from the decimation filter. figure 3 . 31 timing for current , v oltage , and i nternal t emperature m easurements without c hopping for d ifferent c onfigurations of the a verage f ilter startadc conversion result (no avg) ready (no avg) m(t n ) m(t n+1 ) m(t n+2 ) m(t n+3 ) m(t n+4 ) m(t n+5 ) conversion result (2x avg) m(t n ) m(t n+1 ) m(t n+2 ) m(t n+3 ) m(t n+4 ) ready (2x avg) conversion result (3x avg) m(t n ) m(t n+1 ) m(t n+2 ) m(t n+3 ) ready (3x avg) sample rate t s sdmsetup time to fill filter: 4 * t s time to fill filter: 6 * t s time to fill filter: 5 * t s m = measurement; t = time. for current, voltage , or internal temperature measurement without chopping, whe n only one input source must be measured , this is the first valid value. the time when the first valid result is present also depends on the configuration of the average filter ( the avgfiltcfg field in register adcsamp ). if no averaging is used, the first valid value is also the first valid result stored in adccdat , adcvdat, or adctdat . for the 2- stage or 3 - stage average filter, respectively , two or three valid values are needed to calculate a valid result. this adds an addi tional delay , respectively , of 1 or 2 times the sample rate.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 94 april 20, 2016 for external temperature measurement without chopping, two input sources must be measured: the voltage drop over the reference resistor ( the result is stored in register adcrdat ) and the voltage drop over the ntc resistor (result stored in register adctdat ). the sdmsetup time is only introduced at the beginning of the conversion sequence ( the rising edge of startadc ). each single measurement of one of the two values needs 4 times the sample rate w hen averaging is disabled , or respectively , 5 or 6 times the sample rate when using the 2 - stage or 3 - stage average filter. this also means that a complete pair of values used to calculate one external temperature value needs 8 (10 or 12 for averaging) time s the sample rate because for each value , the pipeline of the sinc 4 decimation filter must be filled first. figure 3 . 32 timing for e xternal t emperature m easurements without c hopping when n o a verage f ilter is e nabled startadc conversion result (no avg) ready (no avg) sdmsetup adctdat adcrdat ref_not_ntc m ntc (t n ) m ref (t n ) m ntc (t n+2 ) m ntc (t n+1 ) m ref (t n+1 ) m ref (t n+2 ) m = measurement; t = time. note that using an average filter will lead, respectively, to 5 and 6 conversion results during each hig h and low phase of ref_not_ntc. t he timings shown in the previous two figures are without chopping , which means that the differential input signal is always applied in the same manner to the analog sd - adc. although this kind of measurement is fast (one result value after each sample time), it has the drawback that it also converts any o ffset present in the analog blocks. this would lead to less accurate measurement results. to overcome this, chopping can be enabled (bit chopena in register adcctrl ; see table 3 . 58 ) . when chopping is enabled, the differential input signal is directly applied to the analog sd - adc the first time and inverted the second time. taking this into account in the digital part re moves the offset applied by the adc itself: v 2 ) offset v ( ) 1 ( ) offset v ( data in in in = + - ? - + + = ( 15)
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 95 april 20, 2016 for current, voltage , or internal temperature measurement with c hopping m ode enabled ( chopena set to 1), this leads to a timing similar to the external temperature measurement without chopping and averaging since two values are measured : the normal input and the inverted input. each single measurement of one of the two values needs 4 times the sample rate as no averaging of the single measurement is perfo rmed. instead, the average filter is automatically configured as a 2 - stage average filter to calculate the formula above. the second difference is that a small pause (chopping pause) is introduced each time the chop control signal changes to allow the anal og blocks to settle due to the input change. this is possible since the chopena bit influences both adc paths. the length of the chop pause is either 8 or 16 sdm clock cycles , which can be configured using the choppause bit in register adcsamp. figure 3 . 33 timing for c urrent, v oltage , and i nternal t emperature m easurements using c hopping example shown is for current measurement: startadc c onversion r esult ( chop ) ready ( chop ) sdmsetup chop ctrl m + m + m + m - m - m - adccdat m chp ( t n ) = 0 . 5 *( m + - m - ) m chp ( t n + 1 ) = - 0 . 5 *( m - - m + ) m chp ( t n + 2 ) = 0 . 5 *( m + - m - ) m chp ( t n + 3 ) = - 0 . 5 *( m - - m + ) choppause choppause m = measurement; t = time. for external temperature measurement using chopping, two different input sources must be measured twice, non- inverted and inverted , which leads to four values to be measured to determine a result. to keep both adc paths aligned, the choppause is introduced for each measured value.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 96 april 20, 2016 figure 3 . 34 timing for e xternal t emperature m easurements using c hopping adctdat 0.5*(m + ntc (t n ) - m - ntc (t n )) startadc ready (chop) sdmsetup m + ntc choppause ref_not_ntc chop ctrl conversion result (chop) m + ref m - ntc m - ref m + ntc m + ref m - ntc m - ref 0.5*(m + ntc (t n+1 ) - m - ntc (t n+1 )) adcrdat 0.5*(m + ref (t n ) - m - ref (t n )) m = measurement; t = time. important: the timings only show the principle. additional small delays such as pipeline delays are not included . 3.8.5 diagnostic features 3.8.5.1 adc analog multiplexer control for diagnosis and test in the fp s tate, the three multiplexers shown in figure 3 . 12 can be directly controlled via the register adcchan (see table 3 . 59 ) when the adcmode field in register adcctrl is set to 7 (see table 3 . 58) . for other s ettings of adcmode, the settings of register adcchan are ignored and both multiplexers for input selection are controlled either by the adcmode field in the fp s tate or by the pmu in lp or ulp s tate. the vtsel field in register adcchan is used to select t he input sources of the voltage/temperature adc. the csel field in register adcchan is used to select the input sources of the current adc. important: the reference voltage (non - in verted as well as inverted) can not be measured by the current adc as the mi nimum gain of pga - 2 is 4 , which causes an adc over - range error. for some settings of adcmode, csel, and vtsel , the reference voltage is applied to the adcs. the user can select the source of the reference voltage with the vrefsel field in register adcgomd (see table 3 . 55 ). as can be seen from figure 3 . 12 , the user ?s software can connect internal current s ources to the input wires of the inp and inn pins as well as to the input wires of the nth and ntl pins . to enable the different current sources for the four input wires, the corresponding enable bit in register currentsrcena must be set to 1 (see table 3 . 62). important warning: do not enable both current sources on the same input at the same time. important : the current sources can be enabled independent of the adcmode.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 97 april 20, 2016 3.8.5.2 register ?adcchan? ? analog multiplexer configuration table 3 . 59 register adcchan name address bits default access description vtsel d0 hex [2:0] 0 00 bin rw w hen adcmode == 7, this field selects the different ial source s for the voltage /temperature adc: vtsel inp inn 000 bin vdda nth 001 bin ntl nth 010 bin vptat vbgh (i.e., v ref ) 011 bin vbatp vbatn 100 bin vbgh (i.e., v ref ) vssa 101 bin vbgl (i.e., v reflp ) vssa 110 bin vcm vcm 111 bin high impedance high impedance csel [5:3] 0 00 bin rw w hen adcmode == 7, this field selects the different ial source s for the current adc : 000 bin inp inn 001 bin inp inn 010 bin inp inn 011 bin inp inn 100 bin 1 mv vssa 101 bin unused 110 bin unused 111 bin vcm vcm unused [6] 0 bin rw unused; always write as 0 . u nused [7] 0 bin r w u nused; always write as 0 . 3.8.6 digital features 3.8.6.1 built - in self - test (bist) the digital adc bist feature allows the user to test the digital logic of the adc data path. the bist feature is enabled by setting the bistena bit in register adcdiag to 1 (see table 3 . 61 ) . when the bist feature is enabled, the same programmable bit stream is applied to both inputs of the decimation filter instead of the outputs from the noise cancellation filters. t he adcs mu st also be set into operation as during normal operation. the bit stream to be applied to the decimation filter is programmed to the lower 30 bits of register adccaccth (see table 3 . 44 ). these 30 bits function as a shift - rotate register as shown in figure 3 . 35 , and the output of the lowest bit is us ed as the bit stream for the bist. important: since register adccaccth is used for the bist, the current accumulator threshold functionality cannot be used.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 98 april 20, 2016 figure 3 . 35 usage of r egister adccaccth for the d igital adc bist . . . x x 1 0 1 0 1 0 1 0 29 28 27 26 3 2 1 0 bitstream for bist table 3 . 60 shows four example bit streams as well as the expected output stored in the corresponding dat a registers adccdat, adcvdat, adctdat , and/or adcrdat if enabled . in these examples, the offset correction value ( e.g. , register adccoff ) is set to 0, the gain correction value ( e.g. , register adccgan) is set to 1.0 , and the post correction gain factor ( e.g. , bit field curpocogain [1:0] in register adcpocogain) is set to gain factor 1 ( bit field set to 0 0 bin ) and then to gain factor 2 ( bit field set to 01 bin ). table 3 . 60 example r esults of bist 1/0 bit ratio bit stream result data (xpocogain = gain factor 1, bit field = 00 bin ) result data (xpocogain = gain factor 2, bit field = 01 bin ) 1/6 100000_100000_100000_100000_100000 20820820 hex aaaaaa hex 800000 hex (negative over - range) 5/6 111110_111110_111110_111110_111110 3efbefbe hex 555555 hex 7fffff hex (positive over - range) 2/5 10010_10010_10010_10010_10010_10010 25294a52 hex e66666 hex cccccc hex 3/5 10110_10110_10110_10110_10110_10110 2d6b5ad6 hex 199999 hex 333332 hex 3.8.6.2 decimation filter output test the decimation filter output test allows the user to observe the outputs of both decimation filters. this feature is enabled by setting bit rawena in register adcdiag to 1. when this feature is enabled, the 32 - bit output value of the decimation filter for the current adc is stored in registers adccmax (msbs ; see table 3 . 48 ) and adccmin (lsbs ; see table 3 . 49 ) and the 32 - bit output value of the de cimation filter for the voltage/ temperature adc is stored in registers adcvmax (msbs ; see table 3 . 50 ) and adcvmin (lsbs ; see table 3 . 51 ). t he adcs must also be set into operation as durin g normal operation. note: when this feature is enabled, all normal adc operation s described in the previous section s function as described except the minimum and maximum functionality for the current and voltage values because the registers are used for th is test function. note: this feature can be combined with the digital adc bist feature.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 99 april 20, 2016 3.8.6.3 adc interface test the adc interface test allows the user to observe the incoming 2 nd and 3 rd order bit streams from both analog parts of the sd - adcs. this feature is enabled by setting bit adciftestena in register adcdiag to 1. the digital part of the adc unit must be enabled as for normal operation as it generates the correct sample strobe for t he test logic. this function is only available in the fp s tate as it runs on the 20 mhz clock from the high - precision oscillator. all sampled values (4 bits) are shifted out of the sto pad . to enable the user to synchronize on the sampled data, a 1 and a 0 are shifted out before each 4 - bit value as shown in figure 3 . 36 . figure 3 . 36 b it s tream of adc i nterface t est at sto p ad 2 nd i 2 nd v 3 rd v 3 rd i note: this feature can be combined with the digital adc bist feature and with the decimation filter output test. 3.8.6.4 register ?adcdiag? ? enable register for test and diagnosis features table 3 . 61 register adcdiag name address bits default access description bistena d1 hex [0] 0 bin rw if set to 1, enables bist . rawena [ 1] 0 bin rw if set to 1, enables the decimation filter output test (adc raw data test) . adciftestena [2] 0 bin rw if set to 1, enables the serial adc test . unused [5: 3 ] 0 0 0 bin rw unused; always write as 0. stopclkchop [6] 0 bin rw disable signal for the global chopper (overall analog and digital part chopping). keep this bit ? 0 ? in application if chopping is required. clkchopena [7] 1 bin rw enable signal for internal chopper of the sigma - delta modulator input stage. kee p this bit ?0? in application. 3.8.6.5 register ?currentsrcena? ? enable register for current source table 3 . 62 register currentsrcena name address bits default access description inampinpsrcena d2 hex [0] 0 bin rw enable 50a current source to inp . unused [1] 0 bin rw unused; always write as 0 . inampinnsrcena [2] 0 bin rw enable 50a current source to inn . unused [3] 0 bin rw unused; always write as 0 . psrcenvbat [4] 0 bin rw en able 50a current source on nth. psinkenvbat [5] 0 bin rw enable - 50a current source on nth . nsrcenvbat [6] 0 bin rw enable 50a current source on ntl . nsinkenvbat [7] 0 bin rw enable - 50a current source on ntl .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 100 april 20, 2016 3.9 sbc lin support logic ( for zssc1750 only ) the zssc1750 lin support logic handles two error conditions : a lin domi nant time out on the txd pi n and a short to vbat on the lin pin. figure 3 . 37 illustrates the error protection logic discussed in the next sections. figure 3 . 37 protection l ogic of the lin txd l ine o r & o r txd ( from external mcu ) lin - txd ( lin - phy ) txdprotdis ( register file ) fp state ( pmu ) dettxdtimeout detlinshort 3.9.1 lin wakeup detection a lin master generates a lin wakeup frame by driving a dominant value of 0 of at least 250s on the lin bus. the standard requires that a lin slave must recognize a lin wakeup when the lin bus is low for more than 150s. there is a 6 - bit counter running wi th the 125khz lp clock implemented in the zssc1750 to support the lin wakeup detection. when the function is disabled ( irqen[4] is set to 0), the counter is set to 20 hex and no interrupt can occur. when the function is enabled ( irqen[4] is set to 1), the l in rxd line is observed. when the lin rxd line is high, the counter is set to 00 hex . when the lin rxd line becomes low, the counter is incremented in each clock cycle until it reaches the value 20 hex where it stops incrementing. when the counter is equal t o the programmed wakeup delay (register linwudelay ; see table 3 . 66 ), a set strobe for the corres - ponding interrupt is generated, which causes the syst em to wake up. the register linwudelay has a default value of 14 hex . this setting guarantees that no low level less than 150s on the lin rxd line causes a wakeup due to the inaccuracy of the lp oscillator. 3.9.2 txd timeout detection t he digital lin controller in the external microcontroller must ensure that it does not completely block the lin bus due to continuously transmitting a dominant value of 0. as it is still possible that the txd line from the external microcontroller is stuck at 0 due to a software o r hardware error in the external microcontroller or a broken connection between the external microcontroller and the zssc1750 , the lin support logic observes the txd line in fp s tate to detect if the txd line is erroneously low. the t imeout d etection circu it can handle baud rates down to 1kbaud, where the maximum time that a digital lin controller (slave device!) can transmit a low level is 9 ms (start bit and 8 data bits). to overcome inaccur acies of the internal clocks, the internal logic and untrimmed lin nodes, the timeout value is 10.24 ms.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 101 april 20, 2016 on detection of a txd timeout, an internal flag ( dettxdtimeout in figure 3 . 37 ) is set to the high level , which forces the lin txd line to 1 , and the corresponding interrupt status ( irqstat[2] ) is set. while the interrupt status bit is cleared on read access to the inte rrupt status register, the internal flag remains high , also keeping lin txd at the high level. the status of the internal flag is mirrored in ssw[2] . to clear this internal flag and to be able to transmit again via the lin bus, a value of 1 must be written to bit clrtxdtimeout in register lincfg (see table 3 . 64). 3.9.3 lin short detection the lin phy contains a function to detect a short to vbat on the lin bu s by sensing the current through the open- drain output transistor in the lin phy. when the current is too high, the lin phy drives the short signal going to the digital block to the high level (see figure 3 . 38) . under normal circumstances, the lin phy signals a short only if a dominant value of 0 will be transmitted , but the bus remains at its recessive high level. however , high current consumption is also possible due to emc events. to increase the safety of the system and to avoid misinterpretation, the incoming short signal is gated and filtered. first, the short signal from the lin phy is driven through a configurable gating block inside the digital block. the gating block is configured using register linshortdelay (see table 3 . 65 ). if register linshortdelay is set to a value not equal to 0, the t xd line going to and the rxd line coming from the lin phy are observed. when the txd line becomes low while the rxd line remains high, the gating block waits for linshortdelay times 4 mhz clock cycles before open ing the gate. the gate is closed when either txd becomes high again or rxd becomes low (see figure 3 . 38 ). this feature is used to evalu a te the short signal only when a dominant value of 0 is transmitted , but the bus remains at its recessive high level as well as to eliminate the delay from the txd line through the lin phy back to the rxd line. figure 3 . 38 waveform s howing the g ating p rinciple for n on - zero v alues of linshortdelay txd linshortdelay x 250 ns rxd en gate gated short when the register linshortdelay is set to 0, the gate for the short signal is always open. this means that the short signal is always passed through the gating block even when the txd line is high or the rxd line is low. the gated short signal is applied to a configurable de - bouncing fi lter. this de - bouncing filter is configured using register linshortfilter (see table 3 . 64 ), and it monitors the gated short signal using the internal 4 mhz clock. when the gated short signal is continuously high for ( linshortfilter + 1) clock cycles, the lin short interrupt status bit ( irqstat[3] ) is set , enabling the user?s software running on the connected external microcontroller to respond to this situation. the interrupt status bit is cleared on read access to the interrupt status register.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 102 april 20, 2016 t he software can also enable the hardware to protect the txd line in the case of a detected short condition. when the shortprotena bit in register lincfg (see table 3 . 63 ) is set to 1 and a short condition is detected by the de - bouncing filter, an internal flag ( detlinshort in figure 3 . 37 ) is set to the high level , which forces the lin txd line high . the status of the internal flag is mirrored in ssw[3] . the internal flag remains high until it is explicitly cleared by the software by writing a value of 1 to the clrlinshort bit in register lincfg. 3.9.4 lin testing the lin txd line protection features (txd timeout, lin short, lp s tate ) might restrict the possib ility of testing the lin phy. therefore the protection can be disabled by setting the txdprotdis bit in register lincfg to 1 (see figure 3 . 37) . import ant warning : this must never b e done during normal operation. the ic will not be damaged, but com - munication errors will not be detected. 3.9.4.1 register ?lincfg? ? lin configuration register (zssc1750 only) table 3 . 63 zssc1750 register lincfg important: for the zssc1751 this register is not used and must remain as the default setting. name address bits default access description linfastena b4 hex [0] 0 bin rw w hen set to 1, the slew rate control in the lin phy transmitter is disabled allowing hig her lin data rates of up to 125 kbaud (non - standard feature) . txdprotdis [1] 0 bin rw w hen set to 1, all protection features that force the lin txd line to 1 are overwritten (for test purposes only) . shortprotena [2] 0 bin rw if set to 1, enables the lin short protection . u nused [3] 0 bin ro u nused; always write as 0 . clrtxdtimeout [4] 0 bin rws s trobe register; write 1 to clear the detected txd timeout flag and to release the protection of the lin txd line . clrlinshort [5] 0 bin rws s trobe register; write 1 to clear the detected lin short flag and to release the protection of the lin txd line . u nused [7:6] 0 0 bin ro u nused; always write as 0 .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 103 april 20, 2016 3.9.4.2 register ?linshortfilter? configuration for the lin short de - bounce filter (zssc1750 only) table 3 . 64 zssc1750 register linshortfilter important: for the zssc1751 this register is not used and must remain as the default setting. name address bits default access description linshortfilter b5 hex [7:0] 0f hex rw f ilter configuration for the lin short detector . this register defines the number of 4 mhz clock cycles ( linshortfilter + 1) where the gated lin short signal in the lin phy must be high to detect a short condition on the lin bus. 3.9.4.3 register ?linshortdelay? ? configuration register lin short tx - rx delay (zssc1750 only) table 3 . 65 zssc1750 register linshortdelay important: for the zssc1751 this register is not used and must remain as the default setting. name address bits default access description linshortdelay b6 hex [7:0] 4f hex rw d elay configuration for gating the lin short signal . this register defines the number of 4 mhz clock cycles where txd is low and rxd is high before the gating logic of the lin short signal from the lin phy is removed. when rxd becomes low or txd becomes high, the gating logic is reactivated. note: w hen linshortdelay is set to 0, the txd and rxd levels are ignored and the lin short signal is not gated. 3.9.4.4 register ?linwudelay? ? configuration register for lin wakeup time (zssc1750 only) table 3 . 66 zssc1750 register linwudelay important : for the zssc1751 this register is not used and must remain as the default setting. name address bits default access description linwudelay b7 hex [4:0] 10100 bin rw lin wakeup time. this register defines the number of 125 khz clock cycles where lin - rxd must be low before a lin wakeup conditions is detected. important warning: do not set to 0. unused [7:5] 000 bin ro unused; always write as 0
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 104 april 20, 2016 3.10 zssc1750/51 otp (config register) the zssc1750/51 has an integrated 32x8 bit one - time programmable ( otp ) memory that contains the required trimming data as well as the traceability information. the default (erased) state of the otp cells is 0. because some of the programmed trim b its are critical for operation, such as the voltage trim bits, redundancy is i mple - mented for the lower quarter of the otp memory. this part of the otp contains only up to four bits of information that are programmed to bits [3:0] as well as to bits [7:4]. during the download procedure, the correct content is determined by combining bit 0 and bit 4, bit 1 and bit 5, bit 2 and bit 6 , and bit 3 and bit 7 via an or gate. table 3 . 67 otp memory map name otp a ddress spi a ddress bit range copy to reg . redun - dancy byte order description otp_valid 00 hex e0 hex 0 no yes --- [0]: otp content valid lin_trim 01 hex e1 hex 3: 0 yes yes --- [3:0]: ibias_lin_trim[3:0] vdd_trim 02 hex e2 hex 3: 0 yes yes --- [0]: vddc trim bit [1]: vddp trim bit [3:2]: vbgh_trim[1:0] bg_trim 03 hex e3 hex 3: 0 yes yes --- [3:0]: vbgh_trim[5:2] iref_osc_0 04 hex e4 hex 3: 0 yes yes lsb [3:0]: iref_osc_tc_trim[3:0] iref_osc_1 05 hex e5 hex 3:0 yes yes msb lsb [0]: iref_osc_tc_trim[4] [2]: ibias_lin_trim[4] [3]: iref_osc_trim[0] iref_osc_2 06 hex e6 hex 3:0 yes yes --- [3:0]: iref_osc_trim[4:1] iref_osc_3 07 hex e7 hex 3:0 yes yes msb [3:0]: iref_osc_trim[8:5] iref_lp_osc 08 hex e8 hex 6: 0 yes no --- t rim value for the low - power osc illator adccgan_0 09 hex e9 hex 7: 0 yes no lsb g ain for the current measurement adccgan_1 0a hex ea hex 7:0 yes no --- adccgan_2 0b hex eb hex 7:0 yes no msb adccoff_0 0c hex ec hex 7:0 yes no lsb offset for the current measurement adccoff_1 0d hex ed hex 7:0 yes no --- adccoff_2 0e hex ee hex 7:0 yes no msb adcvgan_0 0f hex ef hex 7:0 yes no lsb gain for the voltage measurement adcvgan_1 10 hex f0 hex 7:0 yes no --- adcvgan_2 11 hex f1 hex 7:0 yes no msb adcvoff_0 12 hex f2 hex 7:0 yes no lsb offset for the voltage measurement adcvoff_1 13 hex f3 hex 7:0 yes no --- adcvoff_2 14 hex f4 hex 7:0 yes no msb adctgan_0 15 hex f5 hex 7:0 yes no lsb gain for the temperature measurement adctgan_1 16 hex f6 hex 7:0 yes no msb adctoff_0 17 hex f7 hex 7:0 yes no lsb offset for the temperature measurement adctoff_1 18 hex f8 hex 7:0 yes no msb --- 19 hex f9 hex --- no no --- u nused
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 105 april 20, 2016 name otp a ddress spi a ddress bit range copy to reg . redun - dancy byte order description lot_id_0 1a hex fa hex 7:0 no no lsb lot id number lot_id_1 1b hex fb hex 7:0 no no msb wafer_no_0 1c hex fc hex 7:0 no no lsb wafer number wafer_no_1 1d hex fd hex 7:0 no no msb die_pos_0 1e hex fe hex 7:0 no no lsb die position die_pos_1 1f hex ff hex 7:0 no no msb after reset of the sbc, the otp download procedure is automatically triggered. first, the otp content s are checked for validity (?bit 0 or bit 4? must be equal to 1). if the content is not valid , the download procedure is stopped. otherwise, the informatio n stored at otp address es 1 to 18 hex is copied into the corresponding registers. the download procedure can also be started by the user by writing the value 1 into the otpdownload bit in register cmdexe (see table 3 . 7 ). special care must be taken after starting the otp downlo ad procedure as the system must not go to the power - down state as long as the download procedure is active. the status of the downl oad procedure is signaled to the user via the ssw bit 0 : the otp download procedure is active when ssw[0] = 1 . in addition to being read by triggering the otp download procedure that copies the otp content s into the corresponding registers, the raw content s of the otp can be read by the user via the spi interface at spi address es e0 hex to ff hex . this might be useful for checking the content s of the otp. for the lowest quarter of the otp , this is useful for checking that no bit has changed its value. t he user might also choose to implement redundancy for the other values by mirroring the content s into th e non volatile memory on the external micro - controller . 3.11 miscellaneous registers 3.11.1.1 register ?pullresena? ? pull - down resistor control register csn, sclk , mosi, txd, trstn, tck, tms , and wdt_dis each contain a configurable internal pull - down resistor that is active by default. the pull - down resistors are present to prevent a floating input pin if the bonding wire is broken and to enable the system to detect such a broken wire or broken connections with the external microcontroller . example: if the bonding wire at txd is broken, the pull - down resistor would drive txd low con tinuously and the lin txd timeout detector will trigger and inform the external microcontroller that an error is present. directly behind the input pins is a secondary protection stage because vddp is disabled in some power - down states. the zssc1750/51 ?s three spi inputs , csn, sclk , and mosi , as well as the txd input , are only enabled in fp s tate . the wdt_dis input is enabled as long as mcu_rstn is high (in the fp or lp s tate) while the zssc1750/51 ?s three test inputs , trstn, tck , and tms , are only enabled when test is high. note: because the test input pin also contains a pull - down resistor, disabling the pull - down resistors for the three test input pins is safe as long as test is low.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 106 april 20, 2016 table 3 . 68 register pullresena name address bits default access description pullresenacsn b8 hex [0] 1 bin rw when set to 1, the pull - down resistor behind the csn pin is connected to the pin . pullresenaspiclk [1] 1 bin rw when set to 1, the pull - down resistor behind the sclk pin is connected to the pin . pullresenamosi [2] 1 bin rw when set to 1, the pull - down resistor behind the mosi pin is connected to the pin . pullresenatxd [3] 1 bin rw when set to 1, the pull - down resistor behind the txd pin is connected to the pin . pullresenatrstn [4] 1 bin rw when set to 1, the pull - down resistor behind the trstn pin is connected to the pin . pullresenatck [5] 1 bin rw when set to 1, the pull - down resistor behind the tck pin is connected to the pin . pullresenatms [6] 1 bin rw when set to 1, the pull - down resistor behind the tms pin is connected to the pin . pullresena wdtdis [7] 1 bin rw when set to 1, the pull - down resistor behind the wdt_dis pin is connected to the pin 3.11.1.2 register ?versioncode? ? version code of sbc the version code of the sbc is 200 hex . table 3 . 69 register versioncode name address bits default access description versioncode[7:0] ba hex [7:0] 0 0 hex ro v ersion code of the sbc . versioncode[11:8] bb hex [3:0] 0010 bin ro u nused [7:4] 000 0 bin ro u nused; always write as 0 .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 107 april 20, 2016 3.11.1.3 register ?pwrtrim? ? trim register for the voltage regulators and bandgap table 3 . 70 register pwrtrim name address bits default access description vddctrim c0 hex [0] 0 bin rw t rim register for vddc regulator : 0 vddc is trimmed to 1.2v 1 vddc is trimmed to 1.8v note: this register is set by the otp download procedure when the otp content is valid . vddptrim [1] 0 bin rw t rim register for the vddp regulator : 0 vddp is trimmed to 2.5v 1 vddp is trimmed to 3.3v note: this register is set by the otp download procedure when the otp content is valid . vbghtrim [7:2] 011111 bin rw t rim register for the high - precision bandgap . note: this register is set by the otp download procedure when otp content is valid . important warning : changing the settings of bits vddctrim and vddptrim c ould cause damage to the connected external microcontroller or caus e it to malfunction! 3.11.1.4 register ?ibiaslintrim? ? trim register for the bias current of the lin block table 3 . 71 register ibiaslintrim name address bits default access description ibiaslintrim c3 hex [4:0] 10000 bin rw t rim register for the bias current of the lin block : 0 smallest value 1 largest value note: this register is set by the otp download procedure when otp content s are valid . u nused [7:5] 0 00 bin ro u nused; always write as 0 .
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 108 april 20, 2016 3.12 voltage regulators in addition to the battery voltage (vbat) , four additional voltage domains are implemented in the zssc1750/51 as described in the following sections . the vdda supply voltage for the analog sections is generated in the vdda_reg block and available on the vdda pin. the vddl voltage for the digital sections during the zssc1750/51?s lp s tate is generated in the lp_reg block and output on the vddl pin , and it can be used as an optional low - power supply f or the external microcontroller. the vddp supply voltage for the sbc?s i/o circuits is generated in the vddp_reg block and output on the vddp pin as an optional supply for the external microcontroller. the vddc supply voltage, an optional supply for the ex ternal microcontroller, is generated in the vddc_reg block and output on the vddc pin . the regulators are low - dro pout regulators (ldo s ) . the vddl regulator , which is active in the low - power states , has very low pow e r consumption. 3.12.1 v dde the following blocks are connected directly to v dde : ? low - power bandgap ? high - precision bandgap ? high - precision oscillator ? por ? regulator for vdda ? regulator for vddl ? regulator for vddc ? regulator for vddp 3.12.2 vbat vbat is the input for the battery voltage measurement using the voltage adc. it is connected to a resistive divider, d ividing vbat to a usable single - ended voltage for the voltage adc (maximum 1.2v) . 3.12.3 vdda the analog regulator provides a 2.5v output and can drive up to 10ma of load current. the output voltage is continuously re gulated with respect to the bandgap voltage (vbgh). a resistor chain generates the appropriate voltage for the feedback comparison with the bandgap voltage so that the correct voltage is generated. this internal regulated voltage serves as a supply voltage for the analog blocks. the analog regulator can be switched off (e.g. , in s leep m ode). the following blocks are connected directly to vdda: ? level - s hifter ? pga ? divider ? temperature m easurement ? sd - adc channel 1 (current) ? sd - adc channel 2 (voltage and temperat ure) ? all blocks necessary for data acquisition (cu rrent, voltage , and temperature measurements )
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 109 april 20, 2016 3.12.4 vddl the vddl regulator provides the supply voltage for the zssc1750/51 ?s digital domain . this regulator remains active in ulp and off s tate s. the following blocks are connected directly to vddl: ? lin phy control (zssc1750 only) ? power m anagement u nit ? all zssc1750/51 registers ? watchdog timer 3.12.5 vddp the peripheral regulator provides 3.3v . the vddp regulator can drive up to 40 ma of load current and can be switche d off (e.g. , in s leep m ode). this voltage is recommended for the supply of the external microcontroller to ensure matching i/o voltage levels as the i / o blocks of the zssc1750/51 are also connected directly to vddp. vddp can be trimmed to the lower range given in specification 1.3.9 using the vddptrim bit field in table 3 . 70. important warning: an improper vddptrim setting could cause damage to the connected external microcontroller or cause it to malfunction! see section 3.3.4 regarding vddp trimming and the reset function. 3.12.6 vddc the core regulator provides 1.8v. this regulator can drive up to 40ma of load current and can be switched off (e.g. , in s leep m ode). this voltage can be used for powering the core of an external microcontroller that requires a lower core voltage than vddp . vddc can be trimmed to the lower range given in specification 1.3.8 using the vddctrim bit field in table 3 . 70. important warning: an improper vddctrim setting could cause damage to the connected external microcontroller or cause it to malfunction!
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 110 april 20, 2016 4 esd / emc the zssc175x is designed to maximize em immunity and minimize emissions. (references to lin communication are only applicable to the zssc1750.) func tional status a: according to specifications; no lin communication errors; memory content must not be lost; no wake - up from sleep mode; no reset. functional status b: according to specifications; offset error extended to < 100ma; no lin communication error s; memory content must not be lost; no wake - up from sleep mode; no reset. functional status c: measurement tolerance beyond specifications; lin communication errors allowed; memory content must not be lost; reset allowed. during em exposure, all functions perform as designed; after exposure, all functions return automatically to within normal limits; memory functions always remain in functional status a. 4.1 electrostatic discharge table 4 . 1 esd protection according to aec - q100 rev. g no. parameter condition min max unit 4.1.1. esd, lin on system level 1) iec 61000 - 4 - 2 6 kv 4.1.2. esd, bat+ on system level 2) iec 61000 - 4 - 2 6 kv 4.1.3. esd, hbm, all other pins aec q 100 - 002 2 kv 4.1.4. esd, cdm, corner pins aec q 100 - 011 750 v 4.1.5. esd, cdm, all other pins aec q 100 - 011 500 v 1) for higher esd levels additional diode is required (see figure 4 1). 2) with external protection d iode gsot36 (see figure 4.1 ) . 4.2 power system ripple factor component functiona lity meets these specification s . u n = 13.5v voltage variation: sine wave amplitude g v = 2v frequency range : 50hz f 25khz (linear sweep width for 10 minutes ) ri of output stage 100m ?
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 111 april 20, 2016 4.3 application circuit examples for emc conformance the f inal application m ight require adaption of the external circuit for emc compliance in the target system as shown in figure 4 . 1 and figure 4 . 2 . figure 4 . 1 optional external components for zssc1750 rbat 100 rinn 22 0 rinp 22 0 rdde 2 . 2 vdde inn vsse vssa inp vpp trstn vdda nth vbat vddp vddc test sleepn vddl lin vssa tms tck sto testl testh vsslin vssn rxd txd mcu _ rstn irqn csn sclk mosi cin 10 0 nf cddl 10 nf rshunt 100 cntc 470 pf ddde bas 2 1 rref 75 k rntc 10 k cdda 470 nf cinn 1 0 nf cinp 1 0 nf cdde 1 10 f cbat 100 nf n . c . rxd chassis gnd bat + bat - tck tms trstn n . c . sto zssc 1750 cdde 2 10 0 nf ntl vss r cddp 2 . 2 f cdd c 2 . 2 f sleepn mcu _ clk wdt _ dis wdt _ dis mcu _ clk miso txd mcu _ rstn irqn csn mosi miso clin 220 pf lin dbat gsot 36 dl in gsot 36 ferrite llin - blm 21 ag 221 sn 1 d or resistor rlin - 20 sclk 1 figure 4 . 2 optional external components for zssc1751 rbat 100 rinn 22 0 rinp 22 0 rdde 2 . 2 vdde inn vsse vssa inp vpp trstn vdda nth vbat vddp vddc test sleepn vddl nc vssa tms tck sto testl testh vss vssn open mcu _ rstn irqn csn sclk mosi cin 10 0 nf cddl 10 nf rshunt 100 cntc 470 pf ddde bas 2 1 rref 75 k rntc 10 k cdda 470 nf cinn 1 0 nf cinp 1 0 nf cdde 1 10 f cbat 100 nf n . c . nc chassis gnd bat + bat - tck tms trstn n . c . sto zssc 1751 cdde 2 10 0 nf ntl vss r cddp 2 . 2 f cdd c 2 . 2 f sleepn mcu _ clk wdt _ dis wdt _ dis mcu _ clk miso mcu _ rstn irqn csn s clk mosi miso nc open vddp dbat gsot 36 1
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 112 april 20, 2016 5 pin configuration and package figure 5 . 1 zssc1750 /51 p qfn36 6x6 mm package pin - out (t op view) exposed pad ( pin 37 ) 1 vdde inn vsse vssa inp vpp trstn vdda nth vbat vddp vddc test sleepn vddl lin vssa tms tck sto testl testh vsslin vssn rxd ntl vss r mcu _ clk wdt _ dis txd mcu _ rstn irqn csn sclk mosi miso 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 27 26 25 24 23 22 21 20 19 36 35 34 33 32 31 30 29 28 zssc 1750 exposed pad ( pin 37 ) 1 vdde inn vsse vssa inp vpp trstn vdda nth vbat vddp vddc test sleepn vddl nc ( 1 ) vssa tms tck sto testl testh vss vssn nc ( 1 ) ntl vss r mcu _ clk wdt _ dis nc ( 1 ) mcu _ rstn irqn csn sclk mosi miso 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 27 26 25 24 23 22 21 20 19 36 35 34 33 32 31 30 29 28 zssc 1751 (1): see table 5.1 for proper pin termination for no - connection (nc) pins . table 5 . 1 zssc1750/ 51 pins description note: see important notes at the end of the table. pin pin n ame type mode description 1 vdde supply input power supply 2 vsse supply input power ground 3 vssa supply input analog voltage ground 4 inp analog input positive input for current channel 5 inn analog input negative input for current channel 6 vssa supply input analog voltage ground 7 vdda analog output analog voltage supply 8 nth analog input positive input for the temperature channel 9 ntl analog input negative input for the temperature channel 10 rxd digital output lin receiver output for zssc1750 only nc n/a n/a not used in zssc1751 ? k eep open 11 txd 1) digital input lin transmitter input for zssc1750 only
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 113 april 20, 2016 pin pin n ame type mode description nc n/a n/a not used in zssc1751 ? c onnect to vddp 12 mcu_rstn digital output reset for external microcontroller 13 irqn digital output interrupt for external microcontroller 14 csn 1) digital input spi chip select 15 sclk 1) digital input spi clock 16 mosi 1) digital input spi master output, slave input 17 miso digital output spi master input, slave output 18 vssn supply input digital voltage ground 19 trstn 1) , 2) digital input test interface 20 tms 1) , 2) digital input test interface 21 tck 1) , 2) digital input test interface 22 sto digital output test interface 23 mcu_clk digital output clock signal to external microcontroller (20mhz) 24 wdt_dis 1) digital input watchdog timer disable pin 25 testl 2) analog in/out test interface 26 testh 2) analog in/out test interface 27 vsslin supply input lin ground for zssc1750 vss supply input power ground for zssc1751 28 lin analog in/out lin bus for zssc1750 nc n/a n/a not used in zssc1751 ? k eep open . 29 vssr supply input power ground 30 vddl analog output sbc digital core supply 31 sleepn digital output sbc power state indicator pin 32 test digital input test interface enable ; c onnect to ground in application 33 vddc analog output external microcontroller supply voltage (core) 34 vddp analog output external microcontroller supply voltage (periphery) 35 vpp analog input otp programming voltage 36 vbat analog input input for battery voltage monitor 37 exposed pad supply input connect to vsse in application 1) digital input with internal pull - down resistor. see parameter r pull_down in table 1.3 . 2) connect to ground in application.
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 114 april 20, 2016 figure 5 . 2 p ackage d rawing of the zssc1750/51 dimensions min (mm) (mm) a 0.8 0.9 a 1 0 0.05 b 0.2 0.3 e 0.5 nom h d 5.9 6.1 h e 5.9 6.1 l 0.45 0.65
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 115 april 20, 2016 6 ordering information product sales code description package zssc1750ea3r zssc1750 battery sensing sbc ? temperature range: -40 c to 125c pqfn36 6x6 mm, reel ZSSC1751EA3R zssc1751 battery sensing sbc ? temperature range: -40 c to 125c pqfn36 6x6 mm, reel zssc1750kit v1.1 zssc1750/51 evaluation kit: modular evaluation and development board for zs sc1750/51, 3 ic samples, and usb cable, (software and documentation can be downloaded from www.idt.com ) 7 related documents document zssc1750/51 feature sheet application notes technical note ? die pad dimensions and coordinates visit the zssc175x product page s at www.idt.com or contact your nearest sales office for the latest version of these documents. 8 glossary term description adc analog - to - digital converter bist built - in self - test dap debug access port ecc error correction code fp full power s tate fsr full scale range ifc current interface ift temp e rature interface its internal temperature sensor lin local interconnect network lp low power state lsb least significant bit or byte depending on context m c u micro c ontroller u nit (external microcontroller) mpx multiplexer mrcs multiple r esults per c onversion s equence
zssc1750 / zssc1751 datasheet ? 2016 integrated device technology, inc. 116 april 20, 2016 term description msb most s ignificant bit nmi non -m askable interrupt ntc negative temperature coefficient otp one - time programmable m emory pa-c preamplifier for current pa-t preamplifier for temperature pga programmable gain amplifier por power - on - reset ppb private peripheral bus ptat proportional to absolute temperature sbc system b asis c hip sdm sigma d elta m odulator spi system packet interface srcs s ingle r esult per c onversion s equence ulp ultra low power s tate 9 document revision history revision date description 1.00 ju ly 10 , 2014 first release. a pril 20 , 2016 changed to idt branding. corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800- 345- 7015 or 408 - 284- 8200 fax: 408 - 284- 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole d iscretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, includin g, but not limited to, the suitability of idt' s products for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey an y license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, a bsent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered tradem arks of idt and its subsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved.

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